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【VHDL-FPGA-Verilog】 simplevhdl DL : 0: 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
Update : 2024-05-02 Size : 4096 Publisher : yvonne
【VHDL-FPGA-Verilog】 shift_register_testbench DL : 0: 16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
Update : 2024-05-02 Size : 23552 Publisher : yeqing
【Other】 debussy11 DL : 0: This the famous hardware testbench technowlege word ,whici name is debussy ,it is helpfull for hardware design-This the famous tech hardware testbench nowlege word, whici name is debussy. it is helpful for hardware design
Update : 2024-05-02 Size : 647168 Publisher : 王明
【VHDL-FPGA-Verilog】 usb11_systemc DL : 0: USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
Update : 2024-05-02 Size : 193536 Publisher : 里晓军
【VHDL-FPGA-Verilog】 usb1_funct DL : 0: usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
Update : 2024-05-02 Size : 52224 Publisher : liuzefu
【Embeded-SCM Develop】 16bit_booth_multiplier_STG DL : 0: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Update : 2024-05-02 Size : 2048 Publisher :
【VHDL-FPGA-Verilog】 ModelSim_TestBench_VHDL DL : 0: ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
Update : 2024-05-02 Size : 1024 Publisher : 汤维
【File Format】 SOC-normal-testbench-and-verification-methology.zi DL : 0: 属于论文的形式，介绍比较详细，在万方数据库中载的，有参考价值-papers belonging to the form, a more detailed briefing, in the popular database contains the reference value
Update : 2024-05-02 Size : 3712000 Publisher : 王嘉
【Books】 VHDL_TESTBENCH DL : 0: 怎样用VHDL写TESTBENCH.rar VHDL仿真-how to use VHDL to write VHDL simulation TESTBENCH.rar
Update : 2024-05-02 Size : 9594880 Publisher : 高
【File Format】 verilog_testbench_preliminary DL : 0: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Update : 2024-05-02 Size : 60416 Publisher : 刘彦
【Linux-Unix】 alu1 DL : 0: alu,原程序及testbench,供初学者参考-alu, the original procedures and testbench and reference for beginners
Update : 2024-05-02 Size : 2048 Publisher : dai hai bo
【Linux-Unix】 register19 DL : 0: register,原程序及testbench,供初学者参考-register, the original procedures and testbench and reference for beginners
Update : 2024-05-02 Size : 3072 Publisher : dai hai bo
【Linux-Unix】 timing19 DL : 0: timing,原程序及testbench,供初学者参考-timing, the original procedures and testbench and reference for beginners
Update : 2024-05-02 Size : 1024 Publisher : dai hai bo
【VHDL-FPGA-Verilog】 cfft DL : 0: 参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
Update : 2024-05-02 Size : 83968 Publisher : wutailiang
【VHDL-FPGA-Verilog】 RISCMCU DL : 0: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Update : 2024-05-02 Size : 594944 Publisher : wutailiang
【VHDL-FPGA-Verilog】 oc8051 DL : 0: 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
Update : 2024-05-02 Size : 1226752 Publisher : wutailiang
【Other Embeded program】 FIFO_v DL : 0: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Update : 2024-05-02 Size : 175104 Publisher : wutailiang
【Software Engineering】 TestBench_writing DL : 0: testbench书写规范格式的ppt教程
Update : 2024-05-02 Size : 20480 Publisher : ZHUOHUI LI
【VHDL-FPGA-Verilog】 systemverilog DL : 1: systemverilog是新出现的一种高级硬件描述和验证语言，这里给出了一些书和文章还有使用vmm方法开发testbench的例子
Update : 2024-05-02 Size : 1608704 Publisher : 闫永志
【VHDL-FPGA-Verilog】 s_fifo DL : 0: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Update : 2024-05-02 Size : 2048 Publisher : 彭帅

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