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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-04-26
  • Size : 5.49mb
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  • Author :dfdqzp
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Introduction - If you have any usage issues, please Google them yourself
ISE ip core cosine sine testbench
Packet file list
(Preview for download)


DDS
...\DDS.gise
...\DDS.xise
...\DDS_CORE.v
...\DDS_CORE_summary.html
...\_ngo
...\....\cs_icon_pro
...\....\...........\_xmsgs
...\....\...........\......\xst.xmsgs
...\....\...........\coregen.cgc
...\....\...........\coregen.cgp
...\....\...........\coregen.log
...\....\...........\generate_icon_pro.xco
...\....\...........\icon_pro.gise
...\....\...........\icon_pro.ucf
...\....\...........\icon_pro.vhd
...\....\...........\icon_pro.vho
...\....\...........\icon_pro.xco
...\....\...........\icon_pro.xise
...\....\...........\icon_pro_flist.txt
...\....\...........\icon_pro_readme.txt
...\....\...........\icon_pro_xmdf.tcl
...\....\...........\tmp
...\....\...........\...\_cg
...\....\...........\...\_xmsgs
...\....\...........\...\......\pn_parser.xmsgs
...\....\cs_ila_pro_0
...\....\............\_xmsgs
...\....\............\......\xst.xmsgs
...\....\............\coregen.cgc
...\....\............\coregen.cgp
...\....\............\coregen.log
...\....\............\generate_ila_pro_0.xco
...\....\............\tmp
...\....\............\...\_cg
...\....\............\...\...\_bbx
...\....\............\...\...\....\_default.lso
...\....\............\...\...\....\chipscope_ila_v1_05_a
...\....\............\...\...\....\.....................\chipscope_ila.vhd
...\....\............\...\...\....\.....................\ila_bram_flat.vhd
...\....\............\...\...\....\.....................\ila_bram_single.vhd
...\....\............\...\...\....\.....................\ila_cap_addrgen.vhd
...\....\............\...\...\....\.....................\ila_cap_ctrl.vhd
...\....\............\...\...\....\.....................\ila_cap_ctrl_g2.vhd
...\....\............\...\...\....\.....................\ila_cap_ctrl_g2_sq.vhd
...\....\............\...\...\....\.....................\ila_cap_storage.vhd
...\....\............\...\...\....\.....................\ila_core.vhd
...\....\............\...\...\....\.....................\ila_match.vhd
...\....\............\...\...\....\.....................\ila_match_combine.vhd
...\....\............\...\...\....\.....................\ila_match_combo.vhd
...\....\............\...\...\....\.....................\ila_match_count.vhd
...\....\............\...\...\....\.....................\ila_match_gand.vhd
...\....\............\...\...\....\.....................\ila_match_gand_srl16.vhd
...\....\............\...\...\....\.....................\ila_match_gandx.vhd
...\....\............\...\...\....\.....................\ila_match_gandx_srl16.vhd
...\....\............\...\...\....\.....................\ila_match_gor.vhd
...\....\............\...\...\....\.....................\ila_match_gorx.vhd
...\....\............\...\...\....\.....................\ila_match_range.vhd
...\....\............\...\...\....\.....................\ila_match_var.vhd
...\....\............\...\...\....\.....................\ila_match_var_srl16.vhd
...\....\............\...\...\....\.....................\ila_match_var_srl32.vhd
...\....\............\...\...\....\.....................\ila_match_varx.vhd
...\....\............\...\...\....\.....................\ila_match_varx_srl32.vhd
...\....\............\...\...\....\.....................\ila_package.vhd
...\....\............\...\...\....\.....................\ila_ram_readaddr.vhd
...\....\............\...\...\....\.....................\ila_reset_ctrl.vhd
...\....\............\...\...\....\.....................\ila_status.vhd
...\....\............\...\...\....\.....................\ila_trace_buffer.vhd
...\....\............\...\...\....\.....................\ila_trig_match.vhd
...\....\............\...\...\....\.....................\ila_trigcond.vhd
...\....\............\...\...\....\.....................\ila_trigcond_lut.vhd
...\....\............\...\...\....\.....................\ila_trigger.vhd
...\....\............\...\...\....\.....................\ila_trigseq_complex.vhd
...\....\............\...\...\....\.....................\ila_trigseq_simple.vhd
...\....\............\...\...\....\chipscope_lib_v1_03_a
...\....\............\...\...\....\.....................\async_deco
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