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【VHDL-FPGA-Verilog】 adder_sub_TB DL : 0: adder/subtractor testbench
Update : 2024-05-17 Size : 1024 Publisher : happywater12
【SCM】 simulation DL : 0: 7segment testbench and velilog
Update : 2024-05-17 Size : 27648 Publisher : happywater12
【SCM】 simulation2 DL : 0: 7segment ctrl testbench and velilog
Update : 2024-05-17 Size : 32768 Publisher : happywater12
【Other】 anc dec DL : 0: encoder,decoder,testbench and run files
Update : 2024-05-17 Size : 27648 Publisher : Gops
【Other】 test DL : 0: 滤波，实现图像的滤波功能的testbench文件，可以适当参考(Filter filtering, testbench file to achieve image filtering function, you can properly refer to)
Update : 2024-05-17 Size : 2048 Publisher : 佳欣—W
【VHDL-FPGA-Verilog】 uygulama1 DL : 0: verilog hdl, haladder testbench
Update : 2024-05-17 Size : 1495040 Publisher : mrv
【VHDL-FPGA-Verilog】 pwm with tb final DL : 0: pwm with testbench in verilog ,synthesizable
Update : 2024-05-17 Size : 189440 Publisher : addy007
【Other】 mycode DL : 0: 这是open silicon interlaken user interface的一个driver,采用的是uvm的架构，能够实现single/dual/quad segment的配置(This is a open silicon Interlaken user interface driver, using the UVM architecture, to achieve the configuration of single/dual/quad segment)
Update : 2024-05-17 Size : 6188032 Publisher : 东哥
【VHDL-FPGA-Verilog】 uart DL : 0: 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
Update : 2024-05-17 Size : 308224 Publisher : 怪了个乖
【Books】 10.1007%2Fs00170-011-3300-z DL : 0: PID controller designed with VHDL,with VHDL testbench code.
Update : 2024-05-17 Size : 348160 Publisher : hlkj,xgh
【VHDL-FPGA-Verilog】 ADC_Data_Recv_Module DL : 0: 接收机测试输入信号，生成正余弦波，采样率、频率、幅度、相位可调节并将生成的数据进行输出压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code)
Update : 2024-05-17 Size : 512000 Publisher : nokkk
【VHDL-FPGA-Verilog】 Clock_Synchronization_Module DL : 0: 数字接收机中频部分数字时钟的设计包括matlab仿真 verilog代码、 testbench代码以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
Update : 2024-05-17 Size : 245760 Publisher : nokkk
【VHDL-FPGA-Verilog】 FFT_Module DL : 1: 接收机数字部分FFT模块的代码包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Update : 2024-05-17 Size : 6002688 Publisher : nokkk
【VHDL-FPGA-Verilog】 Orthogonization_Module DL : 1: 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
Update : 2024-05-17 Size : 1798144 Publisher : nokkk
【VHDL-FPGA-Verilog】 CIC_Filter_Module DL : 1: 数字接收机cic抽取模块抽取倍数可以选择包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
Update : 2024-05-17 Size : 3013632 Publisher : nokkk
【VHDL-FPGA-Verilog】 ezidebug-code DL : 0: Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
Update : 2024-05-17 Size : 339968 Publisher : vickbupt
【VHDL-FPGA-Verilog】 verilog DL : 0: 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
Update : 2024-05-17 Size : 14336 Publisher : wow111
【VHDL-FPGA-Verilog】 float_adder DL : 0: 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
Update : 2024-05-17 Size : 82944 Publisher : 聪明的Jerry
【Other】 1 DL : 0: Hi This is an example of file ZIP Best regards
Update : 2024-05-17 Size : 409600 Publisher : miklk
【VHDL-FPGA-Verilog】 cy7c443 DL : 0: 存储器仿真模型，建立testBench，可对cyc443存储器进行功能仿真。(TestBench memory, can establish simulation model, function simulation of cyc443 memory.)
Update : 2024-05-17 Size : 4096 Publisher : cmic589

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