I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.

testbench
.........\ADPLL.cr.mti
.........\adpll.mpf
.........\ADPLL.v
.........\ADPLL.v.bak
.........\tb_adpll.acf
.........\tb_adpll.hif
.........\tb_ADPLL.v
.........\tb_ADPLL.v.bak
.........\vsim.wlf
.........\work
.........\....\@a@d@p@l@l
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\..........\_primary.vhd
.........\....\tb_@a@d@p@l@l
.........\....\.............\verilog.asm
.........\....\.............\_primary.dat
.........\....\.............\_primary.vhd
.........\....\_info

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．