Search - verilog

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【VHDL-FPGA-Verilog】 cordic-verilog DL : 0: 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
Update : 2024-05-19 Size : 1024 Publisher : 朱子翰
【VHDL-FPGA-Verilog】 uart-code-Verilog DL : 0: uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
Update : 2024-05-19 Size : 10240 Publisher : 李明纬
【VHDL-FPGA-Verilog】 verilog DL : 0: 基于Verilog HDL的通信系统设计一书的电子教案，里面有很多例子，大家可以参考一下-Verilog HDL-based communication system design e-book lesson plans, there are many examples we can refer to
Update : 2024-05-19 Size : 1821696 Publisher :
【VHDL-FPGA-Verilog】 FPGA-verilog DL : 0: 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water lamp experiment, digital pipe display experimentation, etc
Update : 2024-05-19 Size : 10240 Publisher : 星光依旧
【VHDL-FPGA-Verilog】 IEEE.Standard.Verilog.Hardware.Description.Languag DL : 0: IEEE Standard Verilog Hardware Description Language-IEEE Standard Verilog Hardware Description Language(
Update : 2024-05-19 Size : 2178048 Publisher : liukai
【VHDL-FPGA-Verilog】 Testbench(Verilog) DL : 0: verilog验证平台的使用很不错很详细想具体-verilog verification platform is more like using a very good specific
Update : 2024-05-19 Size : 350208 Publisher : guoguo
【VHDL-FPGA-Verilog】 Verilog-vga DL : 0: 基于Verilog的VGA显示汉字、字符的例子以及vga资料-Verilog' s VGA display Chinese characters based on the character of the examples and information vga
Update : 2024-05-19 Size : 1349632 Publisher : 江平
【VHDL-FPGA-Verilog】 Verilog-HDL-2nd-Edition-(Samir-Palnitkar) DL : 1: Verilog HDL 2nd Edition (Samir Palnitkar)
Update : 2024-05-19 Size : 2253824 Publisher : zia
【VHDL-FPGA-Verilog】 Verilog DL : 0: 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
Update : 2024-05-19 Size : 324608 Publisher : LEEY
【VHDL-FPGA-Verilog】 VERILOG-HDL DL : 0: 本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是Verilog HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。 -This book briefly describes the Verilog hardware description language basics, including basic elements of language and basic structure and the use of the language at various levels of digital system modeling. The book lists a large number of examples to help readers master the language itself and the modeling of the actual digital system design is also helpful. Verilog HDL book is a primer for a computer, electronic, electrical and automation related courses and other professional materials are available to the researchers as a reference.
Update : 2024-05-19 Size : 4169728 Publisher : 源泉
【VHDL-FPGA-Verilog】 Verilog-HDL DL : 0: 这是关于VERILOG HDL的有限状态机的源码，大家参考参考，应该有好处的。-This is about VERILOG HDL source code for finite state machines, we refer to the reference, it should be good.
Update : 2024-05-19 Size : 6126592 Publisher : 罗啰
【VHDL-FPGA-Verilog】 Verilog--coding--style DL : 1: Verilog可综合代码编写风格介绍。属于HW中央逻辑开发部的绝密资料，加上本人的总结而成。喷血推荐。-The coding style of Verilog language. It is very useful for verilog system developer
Update : 2024-05-19 Size : 448512 Publisher : liangyao
【VHDL-FPGA-Verilog】 CRC-Generator-for-Verilog-or-VHDL DL : 0: CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
Update : 2024-05-19 Size : 3072 Publisher : wz
【VHDL-FPGA-Verilog】 sdr-sdram-(verilog) DL : 0: Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
Update : 2024-05-19 Size : 777216 Publisher : 左左
【VHDL-FPGA-Verilog】 Verilog-Digital-System DL : 0: Verilog数字系统设计教程-夏宇闻，详细介绍verilog语法及大量范例说明-Verilog Digital System Design Tutorial- Xia Yu Wen
Update : 2024-05-19 Size : 22794240 Publisher : cs
【Internet-Network】 slave-ram-verilog DL : 0: ram代码用verilog写的，有文字说明-verilog code of ram
Update : 2024-05-19 Size : 33792 Publisher : 张明
【VHDL-FPGA-Verilog】 Verilog DL : 0: FPGA经典例子，可以让大家更好的学习Verilog HDL-Classic example of FPGA, allowing you to better learn Verilog HDL
Update : 2024-05-19 Size : 113664 Publisher : 规范
【VHDL-FPGA-Verilog】 verilog-usb--protel-design DL : 1: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Update : 2024-05-19 Size : 53248 Publisher : 唐明桂
【Software Engineering】 verilog-traffic-light DL : 0: 基于VerilogHDL设计的交通灯控制系统本设计利用Verilog HDL 语言、采用层次化混合输入方式,可控制4个路口的红、黄、绿、左转四盏信号灯,让其按特定的规律进行变化。 -This design using Verilog HDL language, adopt hierarchical mixed input method, four intersection control of red, yellow, green, left four lamp lights, let its according to specific rule changes.
Update : 2024-05-19 Size : 98304 Publisher : 镶牙另
【VHDL-FPGA-Verilog】 Verilog-Round-Robin-Arbiter-Model.tar DL : 1: Verilog Round Robin Arbiter Model
Update : 2024-05-19 Size : 1024 Publisher : pippo

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