Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.

verilog
.......\doc
.......\...\readme.txt
.......\...\sdr_sdram.pdf
.......\model
.......\.....\mt48lc8m16a2.v
.......\route
.......\.....\PLL1.v
.......\.....\sdr_sdram.csf
.......\.....\sdr_sdram.esf
.......\.....\sdr_sdram.vqm
.......\simulation
.......\..........\modelsim.ini
.......\..........\readme.txt
.......\..........\sdr_sdram_tb.v
.......\..........\work
.......\..........\....\altclklock
.......\..........\....\..........\verilog.psm
.......\..........\....\..........\_primary.dat
.......\..........\....\..........\_primary.vhd
.......\..........\....\command
.......\..........\....\.......\verilog.psm
.......\..........\....\.......\_primary.dat
.......\..........\....\.......\_primary.vhd
.......\..........\....\control_interface
.......\..........\....\.................\verilog.psm
.......\..........\....\.................\_primary.dat
.......\..........\....\.................\_primary.vhd
.......\..........\....\mt48lc8m16a2
.......\..........\....\............\verilog.psm
.......\..........\....\............\_primary.dat
.......\..........\....\............\_primary.vhd
.......\..........\....\pll1
.......\..........\....\....\verilog.psm
.......\..........\....\....\_primary.dat
.......\..........\....\....\_primary.vhd
.......\..........\....\sdr_data_path
.......\..........\....\.............\verilog.psm
.......\..........\....\.............\_primary.dat
.......\..........\....\.............\_primary.vhd
.......\..........\....\sdr_sdram
.......\..........\....\.........\verilog.psm
.......\..........\....\.........\_primary.dat
.......\..........\....\.........\_primary.vhd
.......\..........\....\sdr_sdram_tb
.......\..........\....\............\verilog.psm
.......\..........\....\............\_primary.dat
.......\..........\....\............\_primary.vhd
.......\..........\....\_info
.......\source
.......\......\altclklock.v
.......\......\Command.v
.......\......\compile_all.v
.......\......\control_interface.v
.......\......\Params.v
.......\......\PLL1.v
.......\......\sdr_data_path.v
.......\......\sdr_sdram.v
.......\synthesis
.......\.........\synplicity
.......\.........\..........\sdr_sdram.prj

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