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Search - verilog - List
【
source in ebook
】
verilog
DL : 0
数字信号处理的FPGA实现(Uwe Meyer-Baese)书中例子的Verilog代码-FPGA implementation of digital signal processing (Uwe Meyer-Baese) book example of Verilog code for
Update
: 2024-05-19
Size
: 330752
Publisher
:
lin
【
Energy industry
】
Verilog
DL : 0
全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
Update
: 2024-05-19
Size
: 3072
Publisher
:
田静
【
VHDL-FPGA-Verilog
】
verilog-counter
DL : 0
利用Verilog实现的数字钟和汽车尾灯,有闹钟,报时,置数等多种功能-Verilog
Update
: 2024-05-19
Size
: 2048
Publisher
:
xzd
【
VHDL-FPGA-Verilog
】
syn-fifo-verilog
DL : 1
用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
Update
: 2024-05-19
Size
: 100352
Publisher
:
runxin218
【
VHDL-FPGA-Verilog
】
sdram-control-verilog
DL : 0
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
Update
: 2024-05-19
Size
: 991232
Publisher
:
runxin
【
Special Effects
】
RGB2YUV(Verilog)
DL : 0
YUV颜色空间转RGB颜色空间,verilog代码实现-YUV to RGB,verilog
Update
: 2024-05-19
Size
: 2048
Publisher
:
蔡玉强
【
Other
】
verilog
DL : 0
verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Update
: 2024-05-19
Size
: 17408
Publisher
:
ddr
【
Other
】
Verilog
DL : 0
无线通信FPGA书籍中的 Verilog代码-the code of the Verilog in the book-wireless communications FPGA
Update
: 2024-05-19
Size
: 131072
Publisher
:
夏宝平
【
VHDL-FPGA-Verilog
】
chengfa-verilog
DL : 0
booth乘法器verilog代码.利用移位和加法来实现乘法-verilog
Update
: 2024-05-19
Size
: 141312
Publisher
:
王林
【
VHDL-FPGA-Verilog
】
Verilog
DL : 0
Verilog 经典教程 初学者必备。很经典的教程-Verilog classic essential tutorial for beginners.
Update
: 2024-05-19
Size
: 1307648
Publisher
:
lli
【
VHDL-FPGA-Verilog
】
VERILOG-jpeg
DL : 0
用Verilog语言在FPGA上实现JPEG图片的解码,附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Update
: 2024-05-19
Size
: 103424
Publisher
:
ken
【
Software Engineering
】
Verilog
DL : 0
Verilog语言学习资料,希望对给为有一点帮助哈-Verilog language learning materials, hoping to have some help on to Kazakhstan
Update
: 2024-05-19
Size
: 593920
Publisher
:
周心驰
【
VHDL-FPGA-Verilog
】
Verilog-HDL
DL : 0
Verilog-HDL实践与应用系统设计-Verilog-HDL Practice and Application System Design
Update
: 2024-05-19
Size
: 15430656
Publisher
:
李秀艳
【
VHDL-FPGA-Verilog
】
Verilog-HDL
DL : 0
《北航常晓明Verilog应用》一书的pdf完整版,是学习Verilog的好书-" Beihang Chang Xiaoming Verilog Applications" pdf full version of the book is a good book to learn Verilog
Update
: 2024-05-19
Size
: 15432704
Publisher
:
甘福连
【
VHDL-FPGA-Verilog
】
verilog
DL : 0
本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器,用Verilog编程首先实现4倍内插,再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
Update
: 2024-05-19
Size
: 4096
Publisher
:
张霄
【
Communication
】
verilog
DL : 0
source code for USB 2.0 fonction core in verilog
Update
: 2024-05-19
Size
: 57344
Publisher
:
chaitanya
【
Other
】
verilog-ieee2001
DL : 0
verilog IEEE标准,学verilog必须要看的资料,将近800页,非常推荐-verilog IEEE standards, learning verilog have to look at the data, nearly 800 pages, very recommended
Update
: 2024-05-19
Size
: 2174976
Publisher
:
huizi
【
source in ebook
】
verilog
DL : 0
大量verilog例程 详细具体 适合于初学者好好学习 -A large number of detailed and specific for verilog routine learn beginner
Update
: 2024-05-19
Size
: 20041728
Publisher
:
胡汗
【
Other
】
ddr-sdram-verilog-resource
DL : 0
描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-description the resource code of ddr_sram
Update
: 2024-05-19
Size
: 896000
Publisher
:
wangyuzhuo
【
VHDL-FPGA-Verilog
】
Verilog
DL : 0
Verilog编写的出租车计价器程序,可以设置按路程计价,按等待时间计价。非常方便,界面良好-Verilog program, prepared a taxi meter can be set according to distance pricing, valuation by waiting time. Very convenient, good interface
Update
: 2024-05-19
Size
: 2170880
Publisher
:
牟星光
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