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Introduction - If you have any usage issues, please Google them yourself
A large number of detailed and specific for verilog routine learn beginner
Packet file list
(Preview for download)
Verilog HDL程序设计\Chapter-1\adder\adder.cr.mti
...................\.........\.....\adder.mpf
...................\.........\.....\adder.v
...................\.........\.....\adder_testbench.do
...................\.........\.....\adder_testbench.v
...................\.........\.....\chart\图1-3.bmp
...................\.........\.....\.....\图1-4.bmp
...................\.........\.....\.....\图1-5.bmp
...................\.........\.....\.....\图1-6.bmp
...................\.........\.....\.....\图1-7.bmp
...................\.........\.....\.....\图1-8.bmp
...................\.........\.....\transcript
...................\.........\.....\vsim.wlf
...................\.........\.....\work\adder\transcript
...................\.........\.....\....\.....\verilog.txt.asm
...................\.........\.....\....\.....\_primary.dat
...................\.........\.....\....\.....\_primary.vhd
...................\.........\.....\....\....._testbench\verilog.asm
...................\.........\.....\....\...............\_primary.dat
...................\.........\.....\....\...............\_primary.vhd
...................\.........\.....\....\_info
...................\.........0\10.2\chart\图10-12.bmp
...................\..........\....\.....\图10-7.bmp
...................\..........\....\.....\图10-8.bmp
...................\..........\....\.....\图10-9.bmp
...................\..........\....\csc.cr.mti
...................\..........\....\csc.mpf
...................\..........\....\csc_testbench.v
...................\..........\....\rgb2ycrcb.v
...................\..........\....\transcript
...................\..........\....\vsim.wlf
...................\..........\....\wave\csc_testbench.bmp
...................\..........\....\....\rgb2ycrcb.bmp
...................\..........\....\.ork\csc_testbench\verilog.asm
...................\..........\....\....\.............\_primary.dat
...................\..........\....\....\.............\_primary.vhd
...................\..........\....\....\rgb2ycrcb\verilog.asm
...................\..........\....\....\.........\_primary.dat
...................\..........\....\....\.........\_primary.vhd
...................\..........\....\....\_info
...................\..........\...3\chart\图10-18.bmp
...................\..........\....\.....\图10-19.bmp
...................\..........\....\.....\图10-20.bmp
...................\..........\....\.....\图10-22.bmp
...................\..........\....\.....\图10-23.bmp
...................\..........\....\.....\图10-25.bmp
...................\..........\....\.....\图10-28.bmp
...................\..........\....\.....\表10-3.bmp
...................\..........\....\dct.cr.mti
...................\..........\....\dct.mpf
...................\..........\....\dct.v
...................\..........\....\dctu.v
...................\..........\....\dctub.v
...................\..........\....\dct_cos_table.v
...................\..........\....\dct_mac.v
...................\..........\....\dct_syn.v
...................\..........\....\dct_testbench.v
...................\..........\....\fdct.v
...................\..........\....\qnr.cr.mti
...................\..........\....\timescale.v
...................\..........\....\transcript
...................\..........\....\vsim.wlf
...................\..........\....\wave\dct.bmp
...................\..........\....\....\dctu.bmp
...................\..........\....\....\dctub.bmp
...................\..........\....\....\dct_testbench.bmp
...................\..........\....\....\fdct.bmp
...................\..........\....\....\zigzag.bmp
...................\..........\....\.ork\bench_top\verilog.asm
...................\..........\....\....\.........\_primary.dat
...................\..........\....\....\.........\_primary.vhd
...................\..........\....\....\dct\verilog.asm
...................\..........\....\....\...\_primary.dat
...................\..........\....\....\...\_primary.vhd
...................\..........\....\....\...u\verilog.asm
...................\..........\....\....\....\_primary.dat
...................\.......
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