Search - verilog

Search - verilog - List

【VHDL-FPGA-Verilog】 verilog-SPI-core DL : 0: 用VerilogHDL写的spi 核的例子-A simple example of SPI core using Verilog HDL
Update : 2024-05-18 Size : 49152 Publisher : guorui
【VHDL-FPGA-Verilog】 DDS-in-Verilog DL : 0: Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
Update : 2024-05-18 Size : 464896 Publisher : haby
【VHDL-FPGA-Verilog】 LVDS-application-Verilog-HDL-code DL : 0: LVDS的应用的Verilog HDL例子程序-LVDS example of the application procedures for the Verilog HDL
Update : 2024-05-18 Size : 421888 Publisher : vico
【VHDL-FPGA-Verilog】 Verilog DL : 0: 比较详细的verilog课件和教程，包括清华的北大的比较实用-More detailed verilog courseware and tutorials, including Tsinghua University Beijing University of more practical
Update : 2024-05-18 Size : 14032896 Publisher : 李永祥
【VHDL-FPGA-Verilog】 verilog DL : 0: 这是一本介绍verilog语言的书籍，verilog语言应用于FPGA，可实现诸多实时处理模块，例如实时OFDM发射机和接收机的制作-verilog for FPGA，real time OFDM Transmitter and receiver
Update : 2024-05-18 Size : 265216 Publisher : k
【VHDL-FPGA-Verilog】 FPGA-RAM-Verilog DL : 0: 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
Update : 2024-05-18 Size : 4847616 Publisher : 何恒盛
【VHDL-FPGA-Verilog】 AHB-BUS-AND-SLAVE-CODE-USING-VERILOG DL : 0: AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
Update : 2024-05-18 Size : 34816 Publisher : xuqinjiang
【VHDL-FPGA-Verilog】 A-Verilog-HDL-Test-Bench-Primer DL : 0: verilog testbench 编写入门，轻松教会编写测试代码-shell interpreter tutorial information, content, round and rich, from the basics
Update : 2024-05-18 Size : 57344 Publisher : 赵玉祥
【VHDL-FPGA-Verilog】 MATLAB-and-verilog DL : 0: 1 采用正弦波，方波进行同步调制，实现调制信号、已调信号、解调信号的波形、频谱以及解调器输入输出信噪比的关系。 2 采用Verilog语言编写有符号的五位乘法器 3 实现数字与模拟调制-A sine wave, square wave synchronous modulation to achieve the modulation signal, the modulated signal, the demodulated signal waveform, spectrum and signal to noise ratio of the demodulator input and output relationship. 2 using Verilog language has signed five digital and analog multiplier 3 modulation
Update : 2024-05-18 Size : 559104 Publisher : 许学真
【VHDL-FPGA-Verilog】 Verilog DL : 0: verilog digital clock
Update : 2024-05-18 Size : 12288 Publisher : mini
【VHDL-FPGA-Verilog】 DAC-use-verilog DL : 0: 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral description
Update : 2024-05-18 Size : 302080 Publisher : 张生
【VHDL-FPGA-Verilog】 ACTEL-FPGA-1602(Verilog) DL : 0: 1602液晶显示程序，用verilog写的！-1602 LCD program, written using verilog!
Update : 2024-05-18 Size : 4096 Publisher : wns
【VHDL-FPGA-Verilog】 QUAD-SPI-verilog DL : 2: 难得的SPI NOR Flash控制器Verilog源代码，支持四路串行通道！-Rare SPI NOR Flash controller Verilog source code, supports four serial channels!
Update : 2024-05-18 Size : 110592 Publisher : david
【VHDL-FPGA-Verilog】 arm-register-verilog DL : 0: 用verilog描述语言实现的4位、32位、arm寄存器。-Verilog description language with 4-bit, 32-bit, arm register.
Update : 2024-05-18 Size : 9393152 Publisher :
【VHDL-FPGA-Verilog】 DDR2-verilog DL : 0: Verilog程序设计实例中，DDR部分的程序代码-Verilog programming example, DDR part of the program code
Update : 2024-05-18 Size : 1221632 Publisher : 林传正
【VHDL-FPGA-Verilog】 Verilog-dds DL : 0: 用Verilog实现的DDS，直接频率合成器，相位可调。-Verilog DDS generator
Update : 2024-05-18 Size : 1184768 Publisher : fu
【VHDL-FPGA-Verilog】 verilog-mac DL : 0: 这是一个以太网的mac程序，verilog写的，可方正可实现-this is a mac implementation using verilog，you can emulate it or implement it directly
Update : 2024-05-18 Size : 128000 Publisher : 王凯
【VHDL-FPGA-Verilog】 verilog--divide-programs DL : 0: verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
Update : 2024-05-18 Size : 578560 Publisher : ni husheng
【VHDL-FPGA-Verilog】 LDPC-Verilog DL : 1: LDPC的verilog程序，含有编解码的过程-LDPC verilog
Update : 2024-05-18 Size : 10844160 Publisher : zhumeng
【VHDL-FPGA-Verilog】 verilog DL : 0: verilog HDL 入门学习的源代码。包括双向语法，计数器，状态机，锁存器，uart等-Introduction to learning verilog HDL source code. Including two-way grammar, counters, state machines, latches, uart, etc.
Update : 2024-05-18 Size : 3072 Publisher : 鲁东

« 1 2 ... 10 11 12 13 14 1516 17 18 19 20 ... 50 »