LVDS example of the application procedures for the Verilog HDL

sim\comp_altera_lib.do
...\comp_gate.do
...\diff_io_top.vo
...\diff_io_top_v.sdo
...\gate_sim.do
...\stratix\@p@r@i@m_@d@f@f@e\verilog.asm
...\.......\.................\_primary.dat
...\.......\.................\_primary.vhd
...\.......\and1\verilog.asm
...\.......\....\_primary.dat
...\.......\....\_primary.vhd
...\.......\....6\verilog.asm
...\.......\.....\_primary.dat
...\.......\.....\_primary.vhd
...\.......\b17mux21\verilog.asm
...\.......\........\_primary.dat
...\.......\........\_primary.vhd
...\.......\.5mux21\verilog.asm
...\.......\.......\_primary.dat
...\.......\.......\_primary.vhd
...\.......\.mux21\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\dffe\verilog.asm
...\.......\....\_primary.dat
...\.......\....\_primary.vhd
...\.......\latch\verilog.asm
...\.......\.....\_primary.dat
...\.......\.....\_primary.vhd
...\.......\mux21\verilog.asm
...\.......\.....\_primary.dat
...\.......\.....\_primary.vhd
...\.......\._cntr\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\nmux21\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\._cntr\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\scale_cntr\verilog.asm
...\.......\..........\_primary.dat
...\.......\..........\_primary.vhd
...\.......\.tratix_asynch_io\verilog.asm
...\.......\.................\_primary.dat
...\.......\.................\_primary.vhd
...\.......\...............lcell\verilog.asm
...\.......\....................\_primary.dat
...\.......\....................\_primary.vhd
...\.......\........crcblock\verilog.asm
...\.......\................\_primary.dat
...\.......\................\_primary.vhd
...\.......\........io\verilog.asm
...\.......\..........\_primary.dat
...\.......\..........\_primary.vhd
...\.......\.........._register\verilog.asm
...\.......\...................\_primary.dat
...\.......\...................\_primary.vhd
...\.......\........jtag\verilog.asm
...\.......\............\_primary.dat
...\.......\............\_primary.vhd
...\.......\........lcell\verilog.asm
...\.......\.............\_primary.dat
...\.......\.............\_primary.vhd
...\.......\............._register\verilog.asm
...\.......\......................\_primary.dat
...\.......\......................\_primary.vhd
...\.......\.........vds_receiver\verilog.asm
...\.......\.....................\_primary.dat
...\.......\.....................\_primary.vhd
...\.......\..............x_parallel_register\verilog.asm
...\.......\.................................\_primary.dat
...\.......\.................................\_primary.vhd
...\.......\.............transmitter\verilog.asm
...\.......\........................\_primary.dat
...\.......\........................\_primary.vhd
...\.......\..............x_out_block\verilog.asm
...\.......\.........................\_primary.dat
...\.......\.........................\_primary.vhd
...\.......\................parallel_register\verilog.asm
...\.......\.................................\_primary.dat
...\.......\.................................\_primary.vhd
...\.......\........mac_mult\verilog.asm
...\.......\................\_primary.dat
...\.......\................\_primary.vhd
...\.......\................_internal\verilog.asm
...\.......\.........................\_primary.dat
...\.......\.........................\_primary.vhd
...\.......\............out\verilog.asm
...\.......\...............\_primary.dat
...\.......\...............\_primary.vhd
...\.......\..............._internal\verilog.asm
...\.......\........................\_primary.dat
...\.......\........................\_primary.vhd
...\.......\............register\verilog.asm
...\.......\....................\_primary.dat
...\.......\....................\_primary.vhd
...\.......\........pll\verilog.asm
...\.......\...........\_primary.dat

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