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【Embeded-SCM Develop】 QuartusII_Versionchinese_new DL : 0: 该编辑器既可以编辑图表模块，又可以编辑原理图 ! 图表模块编辑是主要的顶层设计的主要方法 ! 原理图编辑是传统的设计输入方法 ! 用户可以利用加入Quartus II 提供的LPMs，宏功能等涵数以及用户自己的库涵数来设计 ! 提供“智能”的模块链接和映射-The editor can edit the chart module, but also can edit the schematic! Chart module editor is the main top-level design of the main method! Schematic design editor is a traditional input method! Users can use Quartus II to join provided LPMs, macro functions, etc. Hanjing few, as well as the user s own library to design a few Hanjing! to provide smart module link and mapping
Update : 2024-05-19 Size : 844800 Publisher : Celestia
【VHDL-FPGA-Verilog】 crack-81 DL : 0: 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
Update : 2024-05-19 Size : 14336 Publisher : zxl
【Software Engineering】 07_DDSmokuai DL : 0: DDS模块 EWB Quartus2编译电子综合设计试验箱程序-DDS module EWB Quartus2 chamber compile electronic integrated design process
Update : 2024-05-19 Size : 75776 Publisher : 罗健
【VHDL-FPGA-Verilog】 sine-generator DL : 0: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
Update : 2024-05-19 Size : 675840 Publisher : zzwuyu
【VHDL-FPGA-Verilog】 ug_lpm_rom DL : 0: quartus rom的生成运用matlab生成.mif或.hex文件载入rom表-quartus rom the use of matlab generated generation. mif or. hex file loading rom Table
Update : 2024-05-19 Size : 824320 Publisher : 王欣欣
【VHDL-FPGA-Verilog】 ug_memrom DL : 0: quartus 与 MATLAB 联合仿真，生成rom表，-Quartus joint simulation with MATLAB to generate rom table,
Update : 2024-05-19 Size : 1235968 Publisher : 王欣欣
【VHDL-FPGA-Verilog】 Modelsim DL : 0: modelsim 的使用具体方法与步骤以及与Quartus联合仿真-ModelSim the use of specific methods and procedures, as well as a joint simulation with the Quartus
Update : 2024-05-19 Size : 237568 Publisher : 王欣欣
【VHDL-FPGA-Verilog】 verilog-a DL : 0: verilogA的教材，详细的介绍了语言的用法，主要是用于模拟电路系统建模和仿真。-verilogA materials, detail the usage of the language was mainly used to simulate the circuit system modeling and simulation.
Update : 2024-05-19 Size : 1020928 Publisher : 赵晓迪
【Other】 VerilogHDL DL : 0: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Update : 2024-05-19 Size : 79872 Publisher : sundan
【assembly language】 1234 DL : 0: 多功能数字钟，、在quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
Update : 2024-05-19 Size : 1187840 Publisher : 陈飞
【VHDL-FPGA-Verilog】 fpgacrosslightcontroller DL : 0: fpga交通控制灯，利用quartus 实现，-FPGA traffic control lights, the use of Quartus achieved
Update : 2024-05-19 Size : 3000320 Publisher : 潘敏克
【VHDL-FPGA-Verilog】 yuelao DL : 0: 在QUARTUS II环境下开发的VHDL代码，实现刘德华的歌曲“月老”，本人亲自验证过。-QUARTUS II environment in the development of VHDL code, the realization of Andy Lau s song 月老 , I personally verified.
Update : 2024-05-19 Size : 3072 Publisher : sq
【VHDL-FPGA-Verilog】 QUARTUSoksample DL : 0: 一个完整的QUARTUS设计例子,初学QUARTUS的人必看-Quartus a complete design example, a person must-see novice Quartus
Update : 2024-05-19 Size : 1937408 Publisher : alextuo
【OS Develop】 xapp947 DL : 0: Xilinx FPGA 上FPGA的VxWorks操作系统开发资料-2-Xilinx FPGA on the VxWorks operating system, the development of FPGA information-2
Update : 2024-05-19 Size : 1135616 Publisher : 蓝天
【VHDL-FPGA-Verilog】 quartusII8.0_crack DL : 0: quartusii8.0正式版破解器,正式版可到官网去下载。http://www.altera.com.cn/-quartusii8.0_crack
Update : 2024-05-19 Size : 15360 Publisher : hanhaili
【VHDL-FPGA-Verilog】 Quartus7.2 DL : 0: 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
Update : 2024-05-19 Size : 924672 Publisher : yepp_u2
【VHDL-FPGA-Verilog】 EPM240Prj DL : 0: 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.-This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plus 1 per second. Quartus ii 7.0 use more than open.
Update : 2024-05-19 Size : 521216 Publisher : 白蚁
【Other】 Digitaldisplay DL : 0: 这是利用Quartus II软件设计的数码管显示与控制功能，包括1.无选位的3位显示2.带选位的3位数码管稳定显示3.带有清零和暂停的3位数码管计数 -This is the use of Quartus II software design of digital display and control functions
Update : 2024-05-19 Size : 32768 Publisher : rainbow
【VHDL-FPGA-Verilog】 memory_to_vector DL : 0: 这是一个Quartus的工程文件和verilog代码，讲如何把memory 变成vector-memory to vector
Update : 2024-05-19 Size : 14336 Publisher : 小杨
【VHDL-FPGA-Verilog】 8051 DL : 0: alter公司的mcu核，8051ip核，为quartus2设计，其他应该兼容 -alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
Update : 2024-05-19 Size : 9170944 Publisher : cvdsf

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