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EPM240Prj

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 509kb
  • Downloaded :0次
  • Author :白蚁
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plus 1 per second. Quartus ii 7.0 use more than open.
Packet file list
(Preview for download)
db
..\RoyCPLD.asm.qmsg
..\RoyCPLD.asm_labs.ddb
..\RoyCPLD.cbx.xml
..\RoyCPLD.cmp.cdb
..\RoyCPLD.cmp.hdb
..\RoyCPLD.cmp.logdb
..\RoyCPLD.cmp.rdb
..\RoyCPLD.cmp.tdb
..\RoyCPLD.cmp0.ddb
..\RoyCPLD.dbp
..\RoyCPLD.db_info
..\RoyCPLD.eco.cdb
..\RoyCPLD.fit.qmsg
..\RoyCPLD.hier_info
..\RoyCPLD.hif
..\RoyCPLD.map.cdb
..\RoyCPLD.map.hdb
..\RoyCPLD.map.logdb
..\RoyCPLD.map.qmsg
..\RoyCPLD.pre_map.cdb
..\RoyCPLD.pre_map.hdb
..\RoyCPLD.psp
..\RoyCPLD.pss
..\RoyCPLD.rpp.qmsg
..\RoyCPLD.rtlv.hdb
..\RoyCPLD.rtlv_sg.cdb
..\RoyCPLD.rtlv_sg_swap.cdb
..\RoyCPLD.sgate.rvd
..\RoyCPLD.sgate_sm.rvd
..\RoyCPLD.sgdiff.cdb
..\RoyCPLD.sgdiff.hdb
..\RoyCPLD.signalprobe.cdb
..\RoyCPLD.sld_design_entry.sci
..\RoyCPLD.sld_design_entry_dsc.sci
..\RoyCPLD.syn_hier_info
..\RoyCPLD.tan.qmsg
key.v
led.v
RoyCPLD.asm.rpt
RoyCPLD.cdf
RoyCPLD.done
RoyCPLD.dpf
RoyCPLD.fit.rpt
RoyCPLD.fit.smsg
RoyCPLD.fit.summary
RoyCPLD.flow.rpt
RoyCPLD.map.rpt
RoyCPLD.map.smsg
RoyCPLD.map.summary
RoyCPLD.pin
RoyCPLD.pof
RoyCPLD.qpf
RoyCPLD.qsf
RoyCPLD.qws
RoyCPLD.tan.rpt
RoyCPLD.tan.summary
RoyCPLD.v
rs232_rec_fun.v
rs232_send_fun.v
rs232_speed.v
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