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【VHDL-FPGA-Verilog】 heartbeat DL : 0: 用VHDL编译的源代码，模仿心脏跳动，解压后直接用Quartus打开project即可-Compiled with VHDL source code, mimic the heart beating, after extracting the direct use of Quartus can open the project
Update : 2024-05-19 Size : 547840 Publisher : xie
【VHDL-FPGA-Verilog】 programmablpulsegenerator DL : 0: 用VHDL编译的源代码，可编程脉冲生成器，解压后直接用Quartus打开project即可-Compiled with VHDL source code, programmable pulse generator, after extracting the direct use of Quartus can open the project
Update : 2024-05-19 Size : 13312 Publisher : xie
【VHDL-FPGA-Verilog】 heartbeat DL : 0: 用VHDL编译的源代码，模拟心脏跳动，解压后直接用Quartus打开project即可，不好意思刚才第一个那个模拟心脏跳动（heartbeat）的源程序发错了，请删除，-Compiled with VHDL source code to simulate the beating heart, after extracting the direct use of Quartus can open the project, I am sorry but the first one that simulated beating heart (heartbeat) of the fat source is wrong, please delete
Update : 2024-05-19 Size : 688128 Publisher : xie
【VHDL-FPGA-Verilog】 fourbitincrement DL : 0: 用VHDL编译的源代码，4bit加一器，输入一个4位二进制数自动加一，解压后直接用Quartus打开project即可-Compiled with VHDL source code, 4bit-plus-one, and enter a 4-bit binary number plus one automatically, after extracting the direct use of Quartus can open the project
Update : 2024-05-19 Size : 248832 Publisher : xie
【VHDL-FPGA-Verilog】 Dualpriorityencoder DL : 0: 用VHDL编译的源代码，两位优先级编码器，输入一个十进制数，直接显示头两个‘1’所在的位，解压后直接用Quartus打开project即可-Compiled with VHDL source code, the two priority encoder, enter a decimal number, direct show
Update : 2024-05-19 Size : 359424 Publisher : xie
【Other】 SynplifyPro_QuartusII_Ver5_v4_1 DL : 0: synplify 与quartus 进行FPGA综合设计文档-Synplify and Quartus FPGA integrated design documents for
Update : 2024-05-19 Size : 3281920 Publisher : summery
【VHDL-FPGA-Verilog】 Triangle_Wave_generater DL : 0: 采用vhdl语言编程，基于quartus平台的三角波仿真。-Using VHDL language programming, based on the Quartus triangular wave simulation platform.
Update : 2024-05-19 Size : 2028544 Publisher : 苏苏
【MiddleWare】 seg7_lut_8_0 DL : 0: 七段阴极数码管的FPGA控制程序，开发平台为ISE或者quartus-Seven-Segment LED cathode the FPGA control procedures, development platform for the ISE or Quartus
Update : 2024-05-19 Size : 1024 Publisher :
【VHDL-FPGA-Verilog】 timer_0 DL : 0: 计数器的FPGA控制程序，开发平台为ISE或者quartus-FPGA counter control procedures, development platform for the ISE or Quartus
Update : 2024-05-19 Size : 2048 Publisher :
【VHDL-FPGA-Verilog】 onchip_memory_0 DL : 1: 在线仿真调试的存储器代码，可在ISE或quartus下完成调试-Online simulation of the memory debugging code can be accomplished under the ISE or Quartus debugging
Update : 2024-05-19 Size : 1024 Publisher :
【VHDL-FPGA-Verilog】 jtag_uart_0 DL : 0: jatag在nios环境下的接口代码，可在ISE或quartus下完成调试-Nios jatag environment in the interface code, can be accomplished under the ISE or Quartus debugging
Update : 2024-05-19 Size : 4096 Publisher :
【VHDL-FPGA-Verilog】 cpu_0 DL : 0: cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
Update : 2024-05-19 Size : 302080 Publisher :
【VHDL-FPGA-Verilog】 niosII_system_cpu DL : 0: cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
Update : 2024-05-19 Size : 12288 Publisher :
【VHDL-FPGA-Verilog】 count_binary_0 DL : 0: 二进制计数器的硬件代码，可在ISE或quartus下完成调试-Binary counter hardware code, available at ISE or Quartus to complete debugging
Update : 2024-05-19 Size : 9216 Publisher :
【VHDL-FPGA-Verilog】 20080618101911140 DL : 0: Quartus_II_7.2_b151破解器.用于Quartus_II_7.2-Crack Quartus_II_7.2_b151 browser. For Quartus_II_7.2
Update : 2024-05-19 Size : 403456 Publisher : ellen
【VHDL-FPGA-Verilog】 dxxy DL : 0: 七位巴克码生成代码用vhdl语言编写。将代码复制到quartus里面就可以用了-7 Barker Code generated code using VHDL language. Copy the code inside Quartus can use the
Update : 2024-05-19 Size : 3072 Publisher : lingdu0001
【VHDL-FPGA-Verilog】 chufaqi DL : 0: 这是一个在QUARTUS平台下实现的触发器程序-This is a platform in the Quartus procedures under the flip-flop
Update : 2024-05-19 Size : 2048 Publisher : 李小华
【VHDL-FPGA-Verilog】 Pentium DL : 0: 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
Update : 2024-05-19 Size : 378880 Publisher : citydremer
【VHDL-FPGA-Verilog】 WAVE DL : 0: 关于波形发生功能的Verilog代码和Quartus文件完整文档。-Waveform occurred on the function of Verilog code and Quartus files a complete document.
Update : 2024-05-19 Size : 1409024 Publisher : dan
【Com Port】 uartnew DL : 0: 好用的UART通信源码，使用Verilog 编写在QUARTUS下完成，并用ModelSim仿真通过-Source-to-use UART communications, the use of Verilog in Quartus to complete the preparation and use of ModelSim simulation through
Update : 2024-05-19 Size : 3773440 Publisher : 李伟

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