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【VHDL-FPGA-Verilog】 MAJORITY_VOTER DL : 0: Update : 2024-05-19 Size : 74752 Publisher : 许东滨
【VHDL-FPGA-Verilog】 Example-b3-1 DL : 0: 使用Quartus II设计FPGA的应用设计实例  “\Example-b3-1\uart_regs\src”目录下为设计源文件  “\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块  “\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件  “\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件  “\Example-b3-1\uart_regs\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
Update : 2024-05-19 Size : 397312 Publisher : king
【VHDL-FPGA-Verilog】 UP3_CLOCK DL : 0: 采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。-Using VHDL language UP3 development board electronic bell procedures. Compiled in the Quartus completed.
Update : 2024-05-19 Size : 69632 Publisher : 小毛头
【Other】 czcjjq DL : 1: 使用Quartus II设计并制作一台出租车计价器不同情况具有不同的收费标准行驶公里：在行车三千米以内时，按起步价10元收费，超过3千米部分，以每千米1.6元计算。 l 途中等待（>2min 开始收费）在等待时间小于2分钟以内时不收取额外费用，大于2分钟，按每分钟1.5元计算。-The use of Quartus II design and production of a Taximeter different situations have different criteria for the charges traveling miles: less than 3000 meters in the road when the starting price of 10 yuan by the charges, some more than 3 kilometers to 1.6 kilometers per element calculation. l the way to wait for (
Update : 2024-05-19 Size : 68608 Publisher : yingzhua
【VHDL-FPGA-Verilog】 A8255 DL : 0: 8255的vhdl代码，在Quartus II环境下开发的。-8255 of the VHDL code in Quartus II development environment.
Update : 2024-05-19 Size : 737280 Publisher : 魏杰
【VHDL-FPGA-Verilog】 quartus5.0license DL : 0: quartus5.0license破解码-err
Update : 2024-05-19 Size : 313344 Publisher : 黄景
【VHDL-FPGA-Verilog】 QuartusII DL : 0: 大量VHDL写的数字系统设计有用实例达到-Written by a large number of VHDL digital system design to achieve a useful example
Update : 2024-05-19 Size : 30839808 Publisher : 黄坚
【Other】 TCLscript DL : 0: tcl脚本语言中文教程，可以看看，很不错的哦。-tcl scripting language English tutorial, you can see, very good, oh.
Update : 2024-05-19 Size : 618496 Publisher : 相耀
【VHDL-FPGA-Verilog】 youname DL : 0: 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -Quartus compiler passed with precision frequency meter, etc., I am wrong, but there are several warning (excluding the impact of design). My graduation project ah! ! !
Update : 2024-05-19 Size : 2048 Publisher : luoliwen
【VHDL-FPGA-Verilog】 VHDLFIR DL : 0: VHDL设计FIR滤波器基于QUARTUS和MATLAB-VHDL design of FIR filter based on Quartus and MATLAB
Update : 2024-05-19 Size : 1032192 Publisher : twinslizzy
【Com Port】 openrisc_hello-uart DL : 0: OpenRisc精简版本，uart输出，soc的好材料-OpenRisc streamlined version, uart output, soc good material
Update : 2024-05-19 Size : 789504 Publisher : 万于
【VHDL-FPGA-Verilog】 sditest DL : 0: 基于ep3c25的altera sdi ip核的使用，串并转换和并串转换-Ep3c25 based on the altera sdi ip nuclear use, and conversion and string and string conversion
Update : 2024-05-19 Size : 1477632 Publisher : 林丹
【VHDL-FPGA-Verilog】 quartusii_handbook DL : 0: quartusii 的开发手册,方便quartusii学习-quartusii the development of manuals to facilitate learning quartusii
Update : 2024-05-19 Size : 22112256 Publisher : sun huaiming
【VHDL-FPGA-Verilog】 jiaotdengCPLD DL : 0: 这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。-This is a use of Verilog HDL language program traffic lights. Can be used to run Quartus II.
Update : 2024-05-19 Size : 571392 Publisher : 小李
【VHDL-FPGA-Verilog】 bc_6 DL : 0: 实现6位数据宽度的并串转换，编译和仿真完美实现,编程环境Quartus.
Update : 2024-05-19 Size : 1024 Publisher : kehaiying
【Database system】 DE2_LCD DL : 0: 本源码是用verilog编写控制LCD——使用Quartusii，开发平台使用的是DE2开发板，可实现1602上任意字符显示-The Verilog source code is used to prepare control LCD- the use of Quartusii, development platform using a DE2 development board can realize arbitrary characters show 1602
Update : 2024-05-19 Size : 522240 Publisher : lf
【Other Embeded program】 miaobiaochengxu DL : 0: 利用NIOS和QUARTUS系统完成一个秒表的功能，可以实现正序和倒序显示记录的时间。-Quartus system using NIOS and complete a stopwatch function, can realize positive sequence and the reverse shows record time.
Update : 2024-05-19 Size : 2048 Publisher : 幻婳
【Other Embeded program】 ok DL : 0: quartus下实现的简易人羊白菜过河问题，采用的硬件可能不一样请修改程序中对应的端口-Quartus under the simple people realize sheep cabbage across the river issues, using the same hardware may not modify the procedures corresponding port
Update : 2024-05-19 Size : 250880 Publisher : 刘临政
【GDI-Bitmap】 picturebrowser DL : 0: README for Picturebrowser ========================= The modified files are included as listed in the final report: -alt_ypes.h : header file for io.h -nxview.c: modified this existing, to time the running time of the display -picturebrowser.c: file which handles the logic of buttoons and the driver (button) -hardware (folder): find the project inside and install on the board -jddctmgr.c : modified manager -jdidcint.c: hardware assisted idct transform -Makefile: to compile picturebrowser (you will have to include in romfs to run our project) -io.h -zImage Running our picture viewer: -------------------------- open the project (in hardware folder) with quartus and in programmer install on the board. In the terminal: $ nio2-download -g zImage and the start nios2-terminal $ nios2-terminal at Boot, it detects the USB and run ./pictureviewer Navigate through buttons...enjoy it with moderation:) -README for Picturebrowser ========================= The modified files are included as listed in the final report: -alt_ypes.h : header file for io.h -nxview.c: modified this existing, to time the running time of the display -picturebrowser.c: file which handles the logic of buttoons and the driver (button) -hardware (folder): find the project inside and install on the board -jddctmgr.c : modified manager -jdidcint.c: hardware assisted idct transform -Makefile: to compile picturebrowser (you will have to include in romfs to run our project) -io.h -zImage Running our picture viewer: -------------------------- open the project (in hardware folder) with quartus and in programmer install on the board. In the terminal: $ nio2-download-g zImage and the start nios2-terminal $ nios2-terminal at Boot, it detects the USB and run ./pictureviewer Navigate through buttons...enjoy it with moderation:)
Update : 2024-05-19 Size : 2048 Publisher : slmsw
【VHDL-FPGA-Verilog】 dds_bate4[1].1 DL : 0: 在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。-In the Quartus software using VHDL language realize DDS, can generate sine, cosine, square, triangle and sawtooth waves.
Update : 2024-05-19 Size : 3014656 Publisher : 崔浩然

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