Source-to-use UART communications, the use of Verilog in Quartus to complete the preparation and use of ModelSim simulation through

uartnew
.......\clkdiv.v
.......\clkdiv.v.bak
.......\db
.......\..\prev_cmp_uart_top.asm.qmsg
.......\..\prev_cmp_uart_top.eda.qmsg
.......\..\prev_cmp_uart_top.fit.qmsg
.......\..\prev_cmp_uart_top.map.qmsg
.......\..\prev_cmp_uart_top.tan.qmsg
.......\..\uart_top.asm.qmsg
.......\..\uart_top.cbx.xml
.......\..\uart_top.cmp.bpm
.......\..\uart_top.cmp.cdb
.......\..\uart_top.cmp.ecobp
.......\..\uart_top.cmp.hdb
.......\..\uart_top.cmp.logdb
.......\..\uart_top.cmp.rdb
.......\..\uart_top.cmp.tdb
.......\..\uart_top.cmp0.ddb
.......\..\uart_top.cmp_bb.cdb
.......\..\uart_top.cmp_bb.hdb
.......\..\uart_top.cmp_bb.logdb
.......\..\uart_top.cmp_bb.rcf
.......\..\uart_top.dbp
.......\..\uart_top.db_info
.......\..\uart_top.eco.cdb
.......\..\uart_top.eda.qmsg
.......\..\uart_top.fit.qmsg
.......\..\uart_top.hier_info
.......\..\uart_top.hif
.......\..\uart_top.map.bpm
.......\..\uart_top.map.cdb
.......\..\uart_top.map.ecobp
.......\..\uart_top.map.hdb
.......\..\uart_top.map.logdb
.......\..\uart_top.map.qmsg
.......\..\uart_top.map_bb.cdb
.......\..\uart_top.map_bb.hdb
.......\..\uart_top.map_bb.logdb
.......\..\uart_top.pre_map.cdb
.......\..\uart_top.pre_map.hdb
.......\..\uart_top.psp
.......\..\uart_top.pss
.......\..\uart_top.rtlv.hdb
.......\..\uart_top.rtlv_sg.cdb
.......\..\uart_top.rtlv_sg_swap.cdb
.......\..\uart_top.sgdiff.cdb
.......\..\uart_top.sgdiff.hdb
.......\..\uart_top.signalprobe.cdb
.......\..\uart_top.sld_design_entry.sci
.......\..\uart_top.sld_design_entry_dsc.sci
.......\..\uart_top.syn_hier_info
.......\..\uart_top.tan.qmsg
.......\prev_cmp_uart_top.qmsg
.......\rcvr.v
.......\rcvr.v.bak
.......\simulation
.......\..........\modelsim
.......\..........\........\220model.v
.......\..........\........\altera_mf.v
.......\..........\........\cyclone_atoms.v
.......\..........\........\uart_top.vo
.......\..........\........\uart_top.vo.bak
.......\..........\........\uart_top_modelsim.xrf
.......\..........\........\uart_top_v.sdo
.......\..........\myrproject.cr.mti
.......\..........\myrproject.mpf
.......\..........\project3.cr.mti
.......\..........\project3.mpf
.......\..........\timer_top
.......\..........\.........\pluse_gen
.......\..........\.........\.........\verilog.psm
.......\..........\.........\.........\_primary.dat
.......\..........\.........\.........\_primary.vhd
.......\..........\.........\timer
.......\..........\.........\.....\verilog.psm
.......\..........\.........\.....\_primary.dat
.......\..........\.........\.....\_primary.vhd
.......\..........\.........\timer_tb
.......\..........\.........\........\verilog.psm
.......\..........\.........\........\_primary.dat
.......\..........\.........\........\_primary.vhd
.......\..........\.........\timer_top
.......\..........\.........\.........\verilog.psm
.......\..........\.........\.........\_primary.dat
.......\..........\.........\.........\_primary.vhd
.......\..........\.........\_info
.......\..........\uart_top.xml
.......\..........\uart_top_tb.v
.......\..........\uart_top_tb.v.bak
.......\..........\vsim.wlf
.......\..........\work
.......\..........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
.......\..........\....\..........................................\verilog.psm
.......\..........\....\..........................................\_primary.dat
.......\..........\....\..........................................\_primary.vhd
.......\..........\....\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
.......\..........\....\...............................................\verilog.psm
.......\..........\....\...............................................\_primary.dat
.......\..........\....\...............................................\_primary.vhd

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