Search - bcd

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【Linux-Unix】 ASC_BCD DL : 0: ASCII码和BCD码之间的相互转化源码，在SCO UNIX_SVR5系统下验证通过-ASCII and the BCD conversion
Update : 2024-05-20 Size : 1024 Publisher : liping
【VHDL-FPGA-Verilog】 BCD_7 DL : 0: BCD-7段显示译码器设计 -BCD-7-segment display decoder design
Update : 2024-05-20 Size : 11264 Publisher : FloraChen
【Other】 VHDL_book1 DL : 0: gate：基本逻辑门的实现和验证 mux4_1_gate：多路复用器的门级实现和验证 mux4_1_behav：多路复用器的行为级实现和验证 seg7_gate：7段数码管逻辑门实现和验证 seg7_behav：7段数码管case语句描述和验证 mux7seg：采用按键复用7段数码管的实现和验证 clkseg7：采用时钟自动扫描复用7段数码管的实现和验证 comp4_gate：4位比较器结构化实现和验证 comp8_behav：8位比较器行为实现和验证 decode3_8_gate：3-8译码器的逻辑门实现和验证 decode3_8_behav：3-8译码器的case语句实现和验证 encode8_3_gate：8-3编码器的门级实现和验证 encode8_3_behav：8-3编码器的逻辑门实现和验证 priority_encoder8_3： 8-3优先级编码器的循环语句实现和验证 binbcd4_gate：4位二进制码到BCD码变换设计 binbcd8_behav：8位二进制码到BCD码变换设计 bin_gray4_gate：4位二进制码到Gray码的变换设计 binbcd4_gate：4位Gray码到二进制码变换设计-gate: the realization of basic logic gates and verification mux4_1_gate: multiplexer gate-level implementation and verification mux4_1_behav: Multiplexer behavioral implementation and verification seg7_gate: 7-segment digital tube logic gate implementation and verification seg7_behav: 7 segment digital tube case statements describe and validate mux7seg: using buttons multiplex seven segment LED implementation and verification clkseg7: clock automatically scans using 7-segment digital tube multiplex implementation and verification comp4_gate: 4-bit comparator structured implementation and verification comp8_behav: 8-bit comparator behavior implementation and verification decode3_8_gate :3-8 decoder logic gate implementation and verification decode3_8_behav :3-8 decoder implementation and verification of case statement encode8_3_gate :8-3 encoder gate-level implementation and verification encode8_3_behav :8-3 encoder implementation and verification of logic gates priority_encoder8_3: 8-3
Update : 2024-05-20 Size : 7627776 Publisher : 贾诩
【assembly language】 add DL : 0: 20个8位无符号二进制数求和两个6位的BCD码相减-20 8-bit unsigned binary number summing two 6-digit BCD subtraction
Update : 2024-05-20 Size : 179200 Publisher : 木子
【SCM】 CD4511a7447 DL : 0: 数码管BCD解码驱动器CD4511与7447应用基于80C51单片机Proteus仿真-Digital tube CD4511 BCD decoding drive and 7447 applications, Based on 80 c51 Proteus simulation
Update : 2024-05-20 Size : 23552 Publisher : bellasina
【VHDL-FPGA-Verilog】 BCD_ALU DL : 0: bcd码的ALU单元，包含全加、全减、乘法、除法器-bcd code ALU unit, including All-Canadian, all subtraction, multiplication, division, unit
Update : 2024-05-20 Size : 52224 Publisher : georgeniu
【e-language】 LED_Display DL : 0: Diplay the binary input on a binary to BCD convertes
Update : 2024-05-20 Size : 1024 Publisher :
【SCM】 430-SHILICX DL : 0: 目录：1. 堆栈时钟初始化 2. RAM自测子程序 3. 二进制转化为BCD码（二进制16位（65536）放R15，结果放R4，R5） 4. BCD码转化为二进制（BCD码放R4，二进制放R5） R5=XO+10*(X1+10*(X2+10*X3)) 5. BCD码转化为二进制（BCD码放R4，二进制放R5）R5=XO+10*X1+100*X2+1000*X3 6. 冒泡排序法（适合20个数字以下） 7. X=a^+b^（a为2个字节，b为2个字节，X为3个字节） 8. 比较器的应用 9. 从0X1080H起始的位置写数字，然后读出写入的数字并放在以0X200H开始的位置 10. 采用中断方式，利用TimerA， P1口输出3个不同频率的波形 11. 在比较模式下，使用输出模式7，输出PWM波形 12. CHU32_16除法子程序-Contents: 1. Stack clock initialization 2. RAM self-test routine 3. Binary converted to BCD (binary 16 (65536) put R15, the results put the R4, R5) 4. BCD code into binary (BCD laying R4, binary put R5) R5 = XO+10* (X1+10* (X2+10* X3)) 5. BCD code into binary (BCD laying R4, binary put R5) R5 = XO+10* X1+100* X2+1000* X3 6. bubble sort method (suitable for 20 digits less) 7. X = a ^+b ^ (a is 2 bytes, b is 2 bytes, X is 3 bytes) 8 9 comparator application from writing starting position 0X1080H number and then read out the written numbers and placed in the starting position with 0X200H 10. using interrupt mode, use TimerA, P1 port output three different frequency waveform 11 in Compare mode, using the output mode 7, the output PWM waveform 12 . CHU32_16 division subroutine
Update : 2024-05-20 Size : 3072 Publisher : fzgh
【SCM】 MSP430--16X16 DL : 0: 目录：1. 堆栈时钟初始化 2. RAM自测子程序 3. 二进制转化为BCD码（二进制16位（65536）放R15，结果放R4，R5） 4. BCD码转化为二进制（BCD码放R4，二进制放R5） R5=XO+10*(X1+10*(X2+10*X3)) 5. BCD码转化为二进制（BCD码放R4，二进制放R5）R5=XO+10*X1+100*X2+1000*X3 6. 冒泡排序法（适合20个数字以下） 7. X=a^+b^（a为2个字节，b为2个字节，X为3个字节） 8. 比较器的应用 9. 从0X1080H起始的位置写数字，然后读出写入的数字并放在以0X200H开始的位置 10. 采用中断方式，利用TimerA， P1口输出3个不同频率的波形 11. 在比较模式下，使用输出模式7，输出PWM波形 12. CHU32_16除法子程序-Contents: 1. Stack clock initialization 2. RAM self-test routine 3. Binary converted to BCD (binary 16 (65536) put R15, the results put the R4, R5) 4. BCD code into binary (BCD laying R4, binary put R5) R5 = XO+10* (X1+10* (X2+10* X3)) 5. BCD code into binary (BCD laying R4, binary put R5) R5 = XO+10* X1+100* X2+1000* X3 6. bubble sort method (suitable for 20 digits less) 7. X = a ^+b ^ (a is 2 bytes, b is 2 bytes, X is 3 bytes) 8 9 comparator application from writing starting position 0X1080H number and then read out the written numbers and placed in the starting position with 0X200H 10. using interrupt mode, use TimerA, P1 port output three different frequency waveform 11 in Compare mode, using the output mode 7, the output PWM waveform 12 . CHU32_16 division subroutine
Update : 2024-05-20 Size : 1024 Publisher : fzgh
【VHDL-FPGA-Verilog】 CAL DL : 0: 基于BCD码的十进制ALU设计，可实现加减乘除的功能-BCD to decimal ALU based design can achieve the arithmetic function
Update : 2024-05-20 Size : 16384 Publisher : 任毅
【VHDL-FPGA-Verilog】 BCD_divid_new DL : 0: VHDL语言编写的8位BCD除法器，可以实现浮点数计算，只支持正数运算，并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
Update : 2024-05-20 Size : 525312 Publisher : liudongzhu
【VHDL-FPGA-Verilog】 BCD_subtracter DL : 0: VHDL编写的7位BCD减法器，可实现带小数点减法运算。-VHDL, 7 BCD subtraction, which can be achieved with a decimal point subtraction.
Update : 2024-05-20 Size : 866304 Publisher : liudongzhu
【VHDL-FPGA-Verilog】 Lab2_Part1 DL : 0: display BCD code(0-9) using 7-segment displays in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Update : 2024-05-20 Size : 25600 Publisher : Henna Tan
【VHDL-FPGA-Verilog】 Lab2_Part2 DL : 0: converts a 4-bit binary code to 2-digital BCD code in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Update : 2024-05-20 Size : 112640 Publisher : Henna Tan
【assembly language】 WXZ DL : 0: 加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。常用作计算机算术逻辑部件，执行逻辑操作、移位与指令调用。在电子学中，加法器是一种数位电路，其可进行数字的加法计算。在现代的电脑中，加法器存在于算术逻辑单元（ALU）之中。加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。由于负数可用二的补数来表示，所以加减器也就不那么必要。-The adder is generated the number of and apparatus. Addend and augend input sum and carry bits of the output means is a half adder. If the addend, augend and the low decimal input, and the sum and carry output is a full adder. Commonly used for computer arithmetic logic unit, perform logical operations, shift instruction calls. In electronics, the adder is a digital circuit, which may be a digital sum. In modern computers, the adder is present being in the arithmetic logic unit (ALU). Adder can be used to represent various values , such as: BCD, plus three yards main adder based on binary for computing. Negative two s complement available to represent the addition and subtraction is not so necessary
Update : 2024-05-20 Size : 135168 Publisher : 孙雅琴
【SCM】 wenshidu DL : 0: 温湿度传感器DH11+程序（以SF板为例）[包含单字节二进制转换BCD码程序]-Temperature and humidity sensor DH11+ program (using the SF board, for example) [containing single-byte BCD code binary conversion process]
Update : 2024-05-20 Size : 1068032 Publisher : zhiyun
【VHDL-FPGA-Verilog】 VHDL DL : 0: VHDL小程序，其中包含了bcd码转换成格雷码、寄存器的简单设计（并入串出移位寄存器、串入串出移位寄存器）以及脉冲发生器的VHDL实现。适合于基础的VHDL入门。-VHDL small program, which includes a bcd code into Gray code, register for a simple design (String into a shift register, the string into the string out of the shift register) and a pulse generator VHDL implementation. Suitable for basic VHDL entry.
Update : 2024-05-20 Size : 304128 Publisher : 鸿雨
【Other】 3BCDcounter DL : 0: 该程序为3位BCD计数器，可用于实现0-999循环计数。-The program for the three BCD counters that can be used to implement the loop count 0-999.
Update : 2024-05-20 Size : 4096 Publisher : sky
【VHDL-FPGA-Verilog】 16b_bcd20 DL : 0: 十六位的二进制转为二十位的BCD码，传给大家供大家分享-Sixteen twenty binary into BCD code, passed to everyone for sharing
Update : 2024-05-20 Size : 1024 Publisher : 魏伟东
【Windows Develop】 shijinzhiBCD DL : 0: 十进制－BCD码转换的代码在内，完整希望大家能用上-variable reg : integer range 0 to 80000 variable d1,d2,d3,d4 : std_logic_vector(3 downto 0) begin if clk100 event and clk100= 1 then case current_state1 is when st0=>
Update : 2024-05-20 Size : 84992 Publisher : 追尾事故

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