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【assembly language】 BCD DL : 0: 按键显示不同的显示变化需要配置成独立按键 LED1 EQU 21H LED2 EQU 22H LED3 EQU 23H ORG 00H JMP START START:MOV DPTR,#TABLE MOV LED3,#10H 显示 H 符号 MAIN: MOV A,P3 MOV B,#10H DIV AB MOV LED1,A MOV LED2,B- 按键显示不同的显示变化需要配置成独立按键 LED1 EQU 21H LED2 EQU 22H LED3 EQU 23H ORG 00H JMP START START:MOV DPTR,#TABLE MOV LED3,#10H 显示 H 符号 MAIN: MOV A,P3 MOV B,#10H DIV AB MOV LED1,A MOV LED2,B
Update : 2024-05-20 Size : 1024 Publisher : yoauni
【Software Engineering】 code-led DL : 0: code seven leg module bcd_tang (clock, rst, s1, led) input clock, s1, rst output [6:0] led reg [6:0] led reg [3:0] bcd wire [3:0] bcd_next always @(posedge clock or posedge rst) begin if (rst == 1 b1) begin bcd <= 4 b0 end else if (s1 == 1 b1) begin bcd <= bcd_next // update new value end else begin bcd <= bcd // keep old value end end assign bcd_next = (bcd == 4 b1001) ? 4 b0 : bcd + 1 b1 // bcd : current stage // bcd_next : next stage always @(posedge clock) begin case(bcd) 4 b0000: led <= 7 b1111110 4 b0001: led <= 7 b0110000 4 b0010: led <= 7 b1101101 4 b0011: led <= 7 b1111001 4 b0100: led <= 7 b0110011 4 b0101: led <= 7 b1011011 4 b0110: led <= 7 b1011111 4 b0111: led <= 7 b1110000 4 b1000: led <= 7 b1111111 4 b1001: led <= 7 b1110011 default: led <= 7 b1111111 endcase end endmodule-code seven leg module bcd_tang (clock, rst, s1, led) input clock, s1, rst output [6:0] led reg [6:0] led reg [3:0] bcd wire [3:0] bcd_next always @(posedge clock or posedge rst) begin if (rst == 1 b1) begin bcd <= 4 b0 end else if (s1 == 1 b1) begin bcd <= bcd_next // update new value end else begin bcd <= bcd // keep old value end end assign bcd_next = (bcd == 4 b1001) ? 4 b0 : bcd + 1 b1 // bcd : current stage // bcd_next : next stage always @(posedge clock) begin case(bcd) 4 b0000: led <= 7 b1111110 4 b0001: led <= 7 b0110000 4 b0010: led <= 7 b1101101 4 b0011: led <= 7 b1111001 4 b0100: led <= 7 b0110011 4 b0101: led <= 7 b1011011 4 b0110: led <= 7 b1011111 4 b0111: led <= 7 b1110000 4 b1000: led <= 7 b1111111 4 b1001: led <= 7 b1110011 default: led <= 7 b1111111 endcase end endmodule
Update : 2024-05-20 Size : 194560 Publisher : he
【Other】 bcd_2_asc DL : 0: bcd码转asc码和asc码转bcd码的c语言实现的-asc code asc code bcd codes to turn bcd code c language
Update : 2024-05-20 Size : 3072 Publisher : lucky
【SCM】 DDS485 DL : 0: 单相电能表C源码程序，花了几个月做的单相电能表程序，带485和红外通讯，经过完整功能测试，正常运行。　　代码内有16近制数据转化为BCD、通讯和电量方面的数据存储区数组定义、红外及串口发送定义等。-Single phase energy meter C source programs, and it took a few months to do a single-phase energy meter program, with 485 and infrared communication, complete functional testing, normal operation. Code within 16 nearly made data into the data storage area of the BCD, communication and electricity array definition, infrared and serial port to send the definition.
Update : 2024-05-20 Size : 140288 Publisher : xfjsb
【VHDL-FPGA-Verilog】 Ds18b20_bin2bcd DL : 0: DS18B20数字温度计中小数部分转换BCD码-DS18B20 digital thermometer small number of parts to convert BCD code
Update : 2024-05-20 Size : 2048 Publisher : wenyangzeng
【Software Engineering】 list_ch06_06_bin2bcd DL : 0: Binary-to-BCD conversion circuit
Update : 2024-05-20 Size : 1024 Publisher : owen tsai
【source in ebook】 binBCD DL : 0: bcd码ASIC码的FPGA VHDL实现加仿真-bcd to ASIC in FPGA VHDL
Update : 2024-05-20 Size : 209920 Publisher : 康晓
【Software Engineering】 tools DL : 0: 数值转换，奇偶校验，异或，bcd转asc 等功能，可自己扩展-Numeric conversion, parity, XOR, features such as the bcd turn asc, can expand their own
Update : 2024-05-20 Size : 258048 Publisher : BigZ
【assembly language】 6 DL : 0: 汇编语言，实现指定内存BCD码相乘，结果存放到相应内存中-Assembly language to achieve the specified memory of BCD multiplication results stored in the corresponding memory more than two decimal subtraction can judge the results of the positive and negative
Update : 2024-05-20 Size : 1024 Publisher : 刘宇杰
【Software Engineering】 BCD_ENCODER_Logic_Program DL : 0: Code for BCD Encoder
Update : 2024-05-20 Size : 10240 Publisher : Suyog
【assembly language】 Trabalho1_Thairone DL : 0: Código para projetar contador com decoficador bcd para duplo display de 7 segmentos.
Update : 2024-05-20 Size : 107520 Publisher : Thairone
【SCM】 LjkBCDPlus DL : 0: 自己编写的BCD码加法算法，支持4个字节的数组的BCD运算，如需更多字节，更改for循环控制即可；数据高位放在低地址-Own the BCD adder write algorithm, support 4-byte array BCD arithmetic, high on the low address data more bytes, change the for loop control can be
Update : 2024-05-20 Size : 1024 Publisher : 梁吉坤
【Software Engineering】 bin_to_bcd DL : 0: VHDL之二進制轉BCD碼之程式碼，算完整的-Of binary to BCD code VHDL code, operator complete
Update : 2024-05-20 Size : 69632 Publisher : jj
【assembly language】 transform DL : 0: 完成的功能是将未组合BCD码转换为二进制码，因为未组合BCD码每字节只存放一位BCD数，高半字节为0。所以低位主要采用十位乘10再加上个位的方法，具体通过左移来实现，最后将低位转换结果加上高位实现最终转换。-Complete the function is not BCD code into binary code, because without the combination of BCD codes per byte store only a BCD number, high byte is 0.So low mainly adopts ten bits by 10 plus method on a specific implementation, through the left shift, the low conversion results with high ultimate conversion
Update : 2024-05-20 Size : 1024 Publisher : 陈才燕
【ARM-PowerPC-ColdFire-MIPS】 S8050 DL : 0: S8050详解耗散功率0.625W（贴片：0.3W）集电极电流0.5A集电极--基极电压40V集电极--发射极击穿电压25V集电极-发射极饱和电压 0.6V特征频率fT 最小150MHZ 典型值产家的目录没给出引脚排列为EBC或ECB 838电子按三极管后缀号分为 B C D档贴片为 L H档-S8050 Xiangjie power dissipation 0.625W (SMD: 0.3W) collector current of 0.5A collector- base voltage of 40V collector- emitter breakdown voltage 25V collector- emitter saturation voltage 0.6V characteristic frequency fT the minimum the 150MHZ typical value production home directory is not given pinout EBC or ECB 838 electronic by triode suffix number into BCD file SMD LH file
Update : 2024-05-20 Size : 91136 Publisher : 四真文
【Game Program】 binary-to-bcd2 DL : 0: "二进制数调整BCD码的方法是将二进制码左移8次,每次移位后都检查低四位LSD+3是否大于7,如是则加3,否则不加,高4位MSD作同样处理"-" Binary number to adjust the BCD code is the binary code shifted left eight times, after each shift, check for a low whether four LSD+3 is greater than 7, the case of plus 3, or not added, the high-order 4 bits of MSD same treatment"
Update : 2024-05-20 Size : 11264 Publisher : 王宝
【VHDL-FPGA-Verilog】 bcd7seg DL : 0: program vhdl bcd to 7segment altera de2
Update : 2024-05-20 Size : 261120 Publisher : elen
【Other】 8-channel-temperature DL : 0: 30H：采样高位 31H：采样低位 33H：存储组合的数据，初始化为0 34H35H.36H：组合的BCD码 37H~3CH：分离的BCD码，小数部分作如下处理：将3CH的数据放入3BH中-H: 30 sampling high 31 h: sampling low 33 h: data storage portfolio, initialized to 0 34 h35h. 36 h: combination of BCD 37 h ~ 3 ch: separation of BCD code, and make the following processing: the decimal part 3 ch data to be included in the 3 bh
Update : 2024-05-20 Size : 490496 Publisher : shi
【SCM】 SD2403 DL : 0: 时钟芯片SD2403 驱动，包括BCD码转HEX，读取时间，写入，等-The clock chip SD2403 drive, including BCD to HEX, read time, write
Update : 2024-05-20 Size : 3072 Publisher :
【Picture Viewer】 eda DL : 0: 74LS283的4位BCD码加法器,用quartus2编译，有详细的电路图-74LS283 4-bit BCD counter
Update : 2024-05-20 Size : 142336 Publisher : sai

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