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Lab2_Part1

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-07-22
  • Size : 25kb
  • Downloaded :0次
  • Author :Henna Tan
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
display BCD code(0-9) using 7-segment displays in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Packet file list
(Preview for download)


Lab2_Part1\lab2_part1.asm.rpt
..........\lab2_part1.cdf
..........\lab2_part1.done
..........\lab2_part1.fit.eqn
..........\lab2_part1.fit.rpt
..........\lab2_part1.flow.rpt
..........\lab2_part1.map.eqn
..........\lab2_part1.map.rpt
..........\lab2_part1.pin
..........\lab2_part1.pof
..........\lab2_part1.qpf
..........\lab2_part1.qsf
..........\lab2_part1.qws
..........\lab2_part1.tan.rpt
..........\lab2_part1.tan.summary
..........\lab2_part1.v
..........\seg7.v
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