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Search - verilog - List
【
VHDL-FPGA-Verilog
】
SPtransform
DL : 0
Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
Update
: 2024-05-19
Size
: 1024
Publisher
:
曹光明
【
Other
】
HowtosimulateIPCore
DL : 0
IP核生成器生成 ip 后有两个文件对我们比较有用,假设生成了一个 asyn_fifo 的核,则 asyn_fifo.veo 给出了例化该核方式(或者在 Edit->Language Template->COREGEN 中找到 verilog/VHDL 的例化方式)。asyn_fifo.v 是该核的行为模型,主要调用了 xilinx 行为模型库 的模块,仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Update
: 2024-05-19
Size
: 359424
Publisher
:
任学
【
ELanguage
】
usb_funct
DL : 0
USB接口的VHDL源码,支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
Update
: 2024-05-19
Size
: 230400
Publisher
:
王森
【
VHDL-FPGA-Verilog
】
de_mux
DL : 0
一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
Update
: 2024-05-19
Size
: 40960
Publisher
:
胡东
【
VHDL-FPGA-Verilog
】
mod6_cnt
DL : 0
一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
Update
: 2024-05-19
Size
: 140288
Publisher
:
胡东
【
VHDL-FPGA-Verilog
】
mult8x8
DL : 0
一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Update
: 2024-05-19
Size
: 17408
Publisher
:
胡东
【
Software Engineering
】
risc8
DL : 0
经典计算机体系结构RISC8的源代码(Verilog),包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
Update
: 2024-05-19
Size
: 82944
Publisher
:
snake
【
Special Effects
】
MedianFilter33
DL : 0
3*3 中值滤波的verilog代码实现,已经调试通过!欢迎提出宝贵意见!-3* 3 filtering to achieve the verilog code has been adopted debugging! Welcomed the valuable advice!
Update
: 2024-05-19
Size
: 49152
Publisher
:
【
Other
】
verliog-design
DL : 0
verilog实践教程(包含2个PDF文档)-verilog Practice Guide (including two PDF files)
Update
: 2024-05-19
Size
: 368640
Publisher
:
xuhan
【
Other Embeded program
】
yunsuan-verilog
DL : 0
运算器的实现,即实验指导书中的实验一,文件中包含有原代码及端口设置(可变),用vrilog HDL编程,Xilinx ISE 6仿真,并在实际电路中得到实现.-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Update
: 2024-05-19
Size
: 1600512
Publisher
:
王越
【
ELanguage
】
rs-codec-8-4
DL : 0
encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Update
: 2024-05-19
Size
: 45056
Publisher
:
zs8292
【
VHDL-FPGA-Verilog
】
sdr_c_trl_verilog
DL : 0
SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
Update
: 2024-05-19
Size
: 12288
Publisher
:
曹大壮
【
VHDL-FPGA-Verilog
】
alu_32_bit
DL : 0
verilog 32-bit ALU-verilog 32-bit ALU
Update
: 2024-05-19
Size
: 2048
Publisher
:
qwasqwas
【
MiddleWare
】
pwm_VerilogHDLV1.1
DL : 0
本软件在CPLD上实现数字PWM控制,用Verilog HDL语言编写,在MAX PLUS II调试成功,可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Update
: 2024-05-19
Size
: 232448
Publisher
:
wjz
【
Other Embeded program
】
FPGA_test_frequency
DL : 0
本原码是基于Verilog HDL语言的FPGA原程序,主要用于测频率,特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
Update
: 2024-05-19
Size
: 1024
Publisher
:
jevidyang
【
VHDL-FPGA-Verilog
】
SPI_verilogHDL
DL : 0
本原码是基于Verilog HDL语言编写的,实现了SPI接口设计,可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulation.
Update
: 2024-05-19
Size
: 1024
Publisher
:
jevidyang
【
SCM
】
8051-core
DL : 0
8051单片机是一种应用最广泛的单片机.它的内核设计非常精简,这是用Verilog硬件描述语言写的8051单片机内核-8051 is a most widely used SCM. Its kernel design has been streamlined, This is used Verilog hardware description language to write the 8051 microcontroller core
Update
: 2024-05-19
Size
: 52224
Publisher
:
王二
【
Other
】
Verilog.HDL.A.Guide.To.Digital.Design.And.Synthesi
DL : 0
VHDL的数字设计与综合的经典图书,与大家共享-VHDL digital design and synthesis of the classic books, and share
Update
: 2024-05-19
Size
: 1723392
Publisher
:
张三
【
Editor
】
verilog_source_insight_clf
DL : 0
SOURCE INSIGHT的verilog语法插件,SOURCE INSIGHT支持自动完成等功能,是一个不错的硬件语言编辑分析器-SOURCE INSIGHT verilog syntax of plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers
Update
: 2024-05-19
Size
: 3072
Publisher
:
洪炉
【
Other
】
PerkingUniversityVerilogEducation
DL : 0
北大的Verilog课件。好东东哟-North Verilog courseware. Good Eastern yo
Update
: 2024-05-19
Size
: 1549312
Publisher
:
Simon
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