Search - verilog

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【VHDL-FPGA-Verilog】 CpldandEepromI2c DL : 0: verilog 编写的I2c协议程序，用于cpld读写EEPROM-verilog I2c agreement prepared by the procedures for cpld writable EEPROM
Update : 2024-05-19 Size : 447488 Publisher : 丁明
【Other Embeded program】 div5 DL : 0: 简单的VERILOG五分频电路描述，可综合。已经过检验-simple verilog 0.2-frequency circuit description can be integrated. Have been tested
Update : 2024-05-19 Size : 1024 Publisher : 李四
【VHDL-FPGA-Verilog】 rtl_DRAM DL : 0: 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
Update : 2024-05-19 Size : 4096 Publisher : 明華
【VHDL-FPGA-Verilog】 pci_verilog DL : 1: 一个pci接口的硬件描述语言的实现源代码,用verilog语言实现-a pci interface hardware description language source code to achieve with verilog language
Update : 2024-05-19 Size : 428032 Publisher : 大为
【VHDL-FPGA-Verilog】 riscpu DL : 0: 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
Update : 2024-05-19 Size : 152576 Publisher : 大为
【VHDL-FPGA-Verilog】 fpu DL : 0: 利用FPGA实现浮点运算的verilog代码希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Update : 2024-05-19 Size : 130048 Publisher : jake
【VHDL-FPGA-Verilog】 adder_ahead8bit DL : 0: 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
Update : 2024-05-19 Size : 10240 Publisher : 剑指眉梢
【Other Embeded program】 turbo[1].tar DL : 0: turbo码的verilog程序，有意者请下载。-turbo code verilog procedures Interested parties please download.
Update : 2024-05-19 Size : 84992 Publisher : liu
【VHDL-FPGA-Verilog】 usb_phy DL : 1: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Update : 2024-05-19 Size : 10240 Publisher : liuzefu
【VHDL-FPGA-Verilog】 usb1_funct DL : 0: usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
Update : 2024-05-19 Size : 52224 Publisher : liuzefu
【VHDL-FPGA-Verilog】 simple_fifo DL : 0: verilog HDL原码一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Update : 2024-05-19 Size : 1024 Publisher : zxz
【VHDL-FPGA-Verilog】 verilog_ppt DL : 0: 华为内部的verilog教材的ppt版本。比较详细。-Huawei internal verilog materials ppt version. More detailed.
Update : 2024-05-19 Size : 262144 Publisher : rain6537
【Embeded-SCM Develop】 16bit_booth_multiplier_STG DL : 0: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Update : 2024-05-19 Size : 2048 Publisher :
【Embeded-SCM Develop】 dirital_clock_7 DL : 0: verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
Update : 2024-05-19 Size : 1024 Publisher :
【Embeded-SCM Develop】 dff_UDP DL : 0: verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a description of the fringe is triggered D flip-flop, test test pass
Update : 2024-05-19 Size : 1024 Publisher :
【Embeded-SCM Develop】 I2C_verilog DL : 0: I2C总线verilog实现源码，可以完整实现I2C bus的基本功能-I2C Bus verilog achieving source, I2C bus integrity of the basic functions
Update : 2024-05-19 Size : 20480 Publisher :
【Streaming Mpeg4】 I2C_Controller DL : 0: TW9910初始化程序。verilog。-TW9910 initialization procedures. Verilog.
Update : 2024-05-19 Size : 3072 Publisher : bull
【VHDL-FPGA-Verilog】 risc_spm DL : 0: advanced digital design with the verilog hdl-advanced digital design with the verilog h dl
Update : 2024-05-19 Size : 4096 Publisher : zhenglao
【VHDL-FPGA-Verilog】 PUKverilogPPT1-9PAGE DL : 0: 我收藏的北京大学的verilog的PPT,希望对大家有用,这是1-9章,随后上传剩下的-collection of the Beijing University verilog the PPT, a member of the useful, which is 1-9 chapter Subsequently the remaining Upload
Update : 2024-05-19 Size : 628736 Publisher : 万毅
【VHDL-FPGA-Verilog】 add_16_pipe DL : 0: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Update : 2024-05-19 Size : 1024 Publisher : qjyong

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