Search - verilog

Search - verilog - List

【VHDL-FPGA-Verilog】 Viterbi_v DL : 0: Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
Update : 2024-05-19 Size : 11264 Publisher : qjyong
【VHDL-FPGA-Verilog】 samll DL : 0: 这是一组Verilog的代码小程序，适合新手练习使用．-This is a group of small Verilog code procedures for the use of novice practitioners.
Update : 2024-05-19 Size : 9216 Publisher : 藏瑞
【VHDL-FPGA-Verilog】 firISPdesign DL : 0: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Update : 2024-05-19 Size : 112640 Publisher : xiong
【VHDL-FPGA-Verilog】 Verilog_FPGA_fp DL : 0: 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
Update : 2024-05-19 Size : 124928 Publisher : xiong
【VHDL-FPGA-Verilog】 verilog_latch DL : 0: verilog实现锁存器，共有四个文件，包含测试文件-verilog achieve latches, a total of four documents, including test paper
Update : 2024-05-19 Size : 1024 Publisher : zzm
【VHDL-FPGA-Verilog】 verilogfifo DL : 0: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Update : 2024-05-19 Size : 1024 Publisher : zzm
【VHDL-FPGA-Verilog】 verilog_multiplier DL : 0: verilog实现16*16位乘法器，带测试文件-verilog achieve 16* 16 multiplier, with test documents
Update : 2024-05-19 Size : 25600 Publisher : zzm
【Software Engineering】 VerilogHDLshejifengpingqihe32weijishuqi DL : 0: 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
Update : 2024-05-19 Size : 158720 Publisher : 少华
【Wavelet】 verilogpll1234 DL : 0: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Update : 2024-05-19 Size : 93184 Publisher : li
【VHDL-FPGA-Verilog】 hdb3_verilog DL : 0: modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
Update : 2024-05-19 Size : 22528 Publisher : chengroc
【Other】 I2CbusVHDLVerilogHDL DL : 0: i2c总线verilog源代码，包括测试模块-i2c Bus verilog source code, including testing module
Update : 2024-05-19 Size : 509952 Publisher : 张云凤
【VHDL-FPGA-Verilog】 SimpleSpi DL : 0: master spi的源代码（verilog），包括文档，测试程序-master spi the source code (verilog), including documentation, testing procedures
Update : 2024-05-19 Size : 180224 Publisher : wood
【VHDL-FPGA-Verilog】 Verilog_Development_Board_Sources DL : 0: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Update : 2024-05-19 Size : 3151872 Publisher : Jawen
【Other】 chinese_VerilogHDL DL : 0: Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模，想学习的这个资料对你有用。-Verilog HDL is a hardware description language, for the algorithm level, gate-level to switch-level abstract design of the multiple levels of system modeling, want to study this information be useful to you.
Update : 2024-05-19 Size : 32768 Publisher : 刘斐
【VHDL-FPGA-Verilog】 usb_verilog.tar DL : 1: 文件包含一个usb 专用集成电路设计项目，用的verilog 原码-document contains a usb ASIC design, the original code verilog
Update : 2024-05-19 Size : 197632 Publisher : jockeyhao
【VHDL-FPGA-Verilog】 Verilogmanual DL : 0: VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言-verilog language manuals, and the other enjoying VHDL hardware description language 1
Update : 2024-05-19 Size : 138240 Publisher : 陈度甫
【Other】 VerilogHDL_book DL : 0: Verilog HDL硬件描述语言，徐振林编著。pdf格式。-Verilog HDL Hardware Description Languages, edited cheng. Pdf format.
Update : 2024-05-19 Size : 4841472 Publisher : Zhou
【VHDL-FPGA-Verilog】 simple_cpu DL : 0: 初学cpu结构的很好的verilog代码的示例，适合初学者-novice cpu structure of the good verilog code examples for beginners
Update : 2024-05-19 Size : 79872 Publisher : mapleni
【VHDL-FPGA-Verilog】 sdram_verilog DL : 0: 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
Update : 2024-05-19 Size : 414720 Publisher :
【VHDL-FPGA-Verilog】 traffic2 DL : 0: 用verilog编的小程序,希望对需要的人有所帮助-verilog series with a small procedure, and I hope to the people in need some help
Update : 2024-05-19 Size : 1024 Publisher : 小名

« 1 2 ... 42 43 44 45 46 4748 49 50 »