Search - FPGA

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【ARM-PowerPC-ColdFire-MIPS】 FFT_IP DL : 0: Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
Update : 2024-05-17 Size : 419840 Publisher : zxinkai
【VHDL-FPGA-Verilog】 chengxu(vhdl) DL : 0: 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Update : 2024-05-17 Size : 548864 Publisher : 黄鹏飞
【Other】 EPP_fpga DL : 0: 并口epp模式下与fpga通信例子，附源码-Parallel epp mode communication with the fpga example, enclosure FOSS
Update : 2024-05-17 Size : 1659904 Publisher : 李志刚
【Other】 DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Update : 2024-05-17 Size : 179200 Publisher : 李中伟
【Program doc】 UARTOFFPGA DL : 0: 是关于FPGA/URT原理的一个详细描述.而且里面还有DDAIII实验箱的URT驱动实现.-on FPGA/UTR tenets of a detailed description. But there is also DDAIII experimental box The a172 Drive.
Update : 2024-05-17 Size : 25600 Publisher : 王晓栋
【Other Embeded program】 FPGA_test_frequency DL : 0: 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
Update : 2024-05-17 Size : 1024 Publisher : jevidyang
【VHDL-FPGA-Verilog】 SPI_verilogHDL DL : 0: 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulation.
Update : 2024-05-17 Size : 1024 Publisher : jevidyang
【VHDL-FPGA-Verilog】 mc8051_vhdl DL : 0: mcs51的vhdl IP核,是每个学习FPGA的必经之路，希望一起探讨-mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
Update : 2024-05-17 Size : 394240 Publisher : bluebluewind
【Embeded-SCM Develop】 fpga_ram_flash DL : 0: 一个fpga开发板的原理图，此板具有led灯、ram、flash-an fpga development board diagram, the board has led lights, ram, flash
Update : 2024-05-17 Size : 110592 Publisher : xuyang
【Software Engineering】 testben DL : 0: 这是由xilin公司提供的测试文档，对于用XILINX公司的CPLD/FPGA的用户来说挺不错的。-xilin provided by the test documents, XILINX used for the CPLD/FPGA users quite well.
Update : 2024-05-17 Size : 196608 Publisher : 苏晓利
【VHDL-FPGA-Verilog】 USB11112 DL : 0: USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！-USB vhdl code, which is of great guiding significance. the FPGA control usb helpful!
Update : 2024-05-17 Size : 140288 Publisher : 温暖感
【VHDL-FPGA-Verilog】 modelsim60keygen DL : 0: modsim6破解文件，FPGA开发设计文件资料-modsim6 crack documents, FPGA design development documents
Update : 2024-05-17 Size : 218112 Publisher : 周鸿
【VHDL-FPGA-Verilog】 ps2_vhdl DL : 0: 利用vhdl实现FPGA芯片从PS2键盘读出数据(0-F) 并在数码管上显示 -use FPGA chip from the PS2 keyboard sensed data (0-F) and displayed on a digital control
Update : 2024-05-17 Size : 1024 Publisher : 刘音
【VHDL-FPGA-Verilog】 uart0vhdl DL : 0: vhdl实现fpga和PC机的简单通信(发送),-vhdl achieve fpga and PC simple communication (transmission),
Update : 2024-05-17 Size : 1024 Publisher : 刘音
【Graph Drawing】 VGAsingl DL : 0: fpga显示控制器，利用vhdl语言实现，只能显示8色。-fpga display controller, using vhdl language, the only shows that eight colors.
Update : 2024-05-17 Size : 1024 Publisher : lyc
【VHDL-FPGA-Verilog】 fpu DL : 0: 利用FPGA实现浮点运算的verilog代码希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Update : 2024-05-17 Size : 130048 Publisher : jake
【Other】 c_for_FPGA DL : 0: 最经典的C教程(FPGA编程的),用C语言写的好处这里就不说了-classic C Guide (FPGA Programming), written in C language of the benefits here is not that the
Update : 2024-05-17 Size : 359424 Publisher : 曾某人
【Software Engineering】 fpgapcicom DL : 0: PCI是一种高性能的局部总线规范，可实现各种功能标准的PCI总线卡。本文简要介绍了PCI总线的特点、信号与命令，提出了一种利用高速FPGA实现PCI总线接口的设计方案。 -PCI is a high-performance local bus standard, achievable standards for the various functions of PCI cards. This paper describes the features of the PCI bus, the signal with the order, A proposed high-speed FPGA PCI bus interface design.
Update : 2024-05-17 Size : 474112 Publisher : yaoming
【Software Engineering】 fftfpga DL : 0: 采用按时间抽选的基4原位算法和坐标旋转数字式计算机（CORDIC）算法实现了一个FFT实时谱分析系统。整个设计采用流水线工作方式，保证了系统的速度，避免了瓶劲的出现；整个系统采用FPGA实现，实验表明，该系统既有DSP器件实现的灵活性又有专用FFT芯片实现的高速数据吞吐能力，可以广泛地应用于数字信号处理的各个领域。-time selected by using the in-situ-4 algorithm and coordinate rotation digital computer (CORDIC) algorithm is is a real-time FFT spectrum analysis system. The whole design flow work, to make sure that the speed of the system is to avoid the emergence of fresh bottle; the entire system using FPGA, the experiments show that The system established DSP device with the flexibility of dedicated FFT chips to achieve high-speed data throughput. can be widely applied to the digital signal processing in various fields.
Update : 2024-05-17 Size : 390144 Publisher : yaoming
【VHDL-FPGA-Verilog】 firfpga DL : 0: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Update : 2024-05-17 Size : 228352 Publisher : yaoming

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