Search - FPGA

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【VHDL-FPGA-Verilog】 seg_led_rtl DL : 0: 使用FPGA控制数码管,在数码管上动态的显示数字,很使用,可以直接作为其他模块的子模块,直接调用-FPGA use of digital control in the digital tube dynamic display figures that use, direct module as other sub-module, called directly
Update : 2024-05-17 Size : 7168 Publisher : wpb3dm
【VHDL-FPGA-Verilog】 pro001_buzzer DL : 0: 使用FPGA控制蜂鸣器的程序,用Verilog HDL设计,可以是蜂鸣器发出各种不同的声音-FPGA use buzzer control procedures, using Verilog HDL design, it is the buzzer sounded different voices
Update : 2024-05-17 Size : 779264 Publisher : wpb3dm
【Program doc】 FPGA_syn_design DL : 0: FPGA同步设计技术,对在FPGA设计中出现的同步问题,毛刺的处理等问题,给出了相应的对策-synchronous FPGA design technology, in FPGA design the synchronization problem, the handling of Burr, given the corresponding countermeasures
Update : 2024-05-17 Size : 169984 Publisher : wpb3dm
【VHDL-FPGA-Verilog】 serial_VHDL DL : 0: FPGA进行串口通信的程序 VHDL编写的 -FPGA for serial communication procedure prepared by the VHDL
Update : 2024-05-17 Size : 2048 Publisher : 饮血病
【VHDL-FPGA-Verilog】 videodigitalsignalscontroller DL : 1: 用fpga技术实现基本的视频信号处理：主题程序；视频图象数据采集程序；sram的读写控制；测试程序-they simply use the basic technology of video signal processing : theme; Video data acquisition procedures; SRAM literacy control; test procedures
Update : 2024-05-17 Size : 8192 Publisher : yan
【VHDL-FPGA-Verilog】 200512251221612004 DL : 0: 本文件是altera公司fpga的ip核，从国外网站下载的免费源码。-ALTERA This document is the company they simply ip nuclear, downloaded from the web free source.
Update : 2024-05-17 Size : 787456 Publisher : 崔战
【ARM-PowerPC-ColdFire-MIPS】 AUDIO_DAC DL : 0: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Update : 2024-05-17 Size : 2048 Publisher : 赵春生
【STL】 FIRDATA DL : 0: FIR 数字滤波器分布式算法及其FPGA实现-FIR digital filter algorithms and FPGA
Update : 2024-05-17 Size : 30720 Publisher : ankerbb
【Post-TeleCom sofeware systems】 iir_filters DL : 0: 说明：这个代码是基于FPGA的数字IIR无限长冲激响应滤波器的源代码．-Note : This code is based on the number of FPGA IIR infinite impulse response filter the source code.
Update : 2024-05-17 Size : 1024 Publisher : 李军
【VHDL-FPGA-Verilog】 Altera_uart_VHDL DL : 0: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA/CPLD applications, UART communications VHDL source.
Update : 2024-05-17 Size : 10240 Publisher : cyberworm
【VHDL-FPGA-Verilog】 Altera_uart_Verilog DL : 0: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Update : 2024-05-17 Size : 10240 Publisher : cyberworm
【VHDL-FPGA-Verilog】 source_files DL : 0: FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
Update : 2024-05-17 Size : 7168 Publisher : tanbo
【Static control】 clock2001 DL : 0: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
Update : 2024-05-17 Size : 1024 Publisher : dandan
【MiddleWare】 beipin_quartII DL : 0: 在FPGA或CPLD上实现的一中非常实用的倍频电路，只要输入频率高，精度就很高-the CPLD or FPGA to achieve a very practical frequency circuit, as long as the input frequency, on the high precision
Update : 2024-05-17 Size : 75776 Publisher : 王石子
【Embeded Linux】 elphel_6.2.12.tar DL : 0: 基于FPGA的IP camera的开源系统-FPGA-based IP camera open source system
Update : 2024-05-17 Size : 1814528 Publisher : xiao
【Compress-Decompress algrithms】 color_proc333 DL : 0: 基于fpga的MJPEG编码,用硬件描述语言vlogic写的-they simply based on the JPEG coding, using hardware description language to write the vlogic
Update : 2024-05-17 Size : 10240 Publisher : xiao
【VHDL-FPGA-Verilog】 xapp290 DL : 0: 从Xilinx网站上下的，学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.
Update : 2024-05-17 Size : 2553856 Publisher : sk
【Software Engineering】 cpld_line_cnc DL : 0: 关于用CPLD和FPGA做插补算法的内容,对于想用FPGA做控制的朋友是个好的借鉴!-on with CPLD and FPGA done interpolation algorithm, for to do with the control of the FPGA is a good friend from!
Update : 2024-05-17 Size : 191488 Publisher : 舟舟
【VHDL-FPGA-Verilog】 FPGAUART DL : 0: 一个基于FPGA的串口程序,已经经过验证,对用FPGA做串口的朋友提供参考和借鉴!-an FPGA-based serial procedures have proven, right Serial do with FPGA reference for a friend and borrow!
Update : 2024-05-17 Size : 311296 Publisher : 舟舟
【Other】 fpedit DL : 0: Xilinx FPGA 开发软件ISE中的FPGA Edit使用方法详细介绍-Xilinx FPGA development software ISE FPGA Edit the use of detailed
Update : 2024-05-17 Size : 813056 Publisher : sk

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