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【WEB Code】 V4ML450usersguide DL : 0: xilinx的嵌入式开发xps，virtex-4的450开发板用户手册-Xilinx Embedded Development xps, Virtex-4 of 450 development board user manual
Update : 2008-10-13 Size : 707447 Publisher : 王前
【WEB Code】 v4DSPusersguide DL : 0: xilinx的嵌入式开发xps，virtex-4的dsp发板用户手册-Xilinx Embedded Development xps, Virtex-4 dsp the board user manual
Update : 2008-10-13 Size : 637576 Publisher : 王前
【Other resource】 S2P_xapp194 DL : 0: VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
Update : 2008-10-13 Size : 27291 Publisher : 苏翔
【Com Port】 manchester_base_on_verilog DL : 0: yon用硬件描述语言写的曼彻斯特编解码,并在Xilinx CPLD上的实现,内容齐全,是学习的好资料-yon hardware description language used to write the Manchester encoding and decoding Xilinx CPLD and the realization that the complete study is a good information
Update : 2008-10-13 Size : 10267 Publisher : slam
【Other resource】 FPGA_download_sch DL : 0: Xilinx公司的FPGA下载电路连接原理图，对初学EDA者应该有所帮助。-company Xilinx FPGA download circuit diagram of a novice EDA should help.
Update : 2008-10-13 Size : 47725 Publisher : 张剑
【Other】 taxiwork DL : 0: 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计，并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分，整个自动控制系统由四个模块构成：秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能，其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程、计费准确可靠，应用于实际当中有较好的实用价值和较高的可行性。-introduced FPGA-based multifunctional taxi meter circuit design. The design using programmable logic device FPGA ASIC design, and for the super-high-speed VHDL hardware description language in the company Xilinx Spartan II Series 2 sc 200PQ208-5 chip programming of the control system as a whole, Automatic control the entire system from four modules : a seconds-frequency module, control module, metrology modules and decoding module. The design not only achieved a taxi showed Billing functions, Multifunctional its performance through its keypad revealed taxi taking the cumulative total journey of the passengers took the set time. Program, log, billing is accurate, reliable and practical application of them have good practical value and the higher the possibility.
Update : 2008-10-13 Size : 9090 Publisher : 柑佬
【Other resource】 xapp616 DL : 0: A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
Update : 2008-10-13 Size : 13454 Publisher : 窦洪山
【Other resource】 System09 DL : 0: BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module-BurchED B5 - X300 Spartan2e using XC2S300e Top level device file for 6809 compatible syste m on a chip Designed with Xilinx XC2S300e Sparta n 2 FPGA. Implemented With BurchED B5 - X300 FPGA board, B5-SRAM module, B5-CF module and B5 - FPGA-CPU-IO module
Update : 2008-10-13 Size : 610666 Publisher : 陈朋
【Other】 ISPdownload DL : 0: 各种JTAG：包括ALTERA、ARM、AVR、LATTICE、S52、XILINX。-various JTAG include : Altera, ARM, AVR, LATTICE, S52, XILINX.
Update : 2008-10-13 Size : 182815 Publisher : 郭shaojia
【Other resource】 VerilogHDLPLI DL : 0: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Update : 2008-10-13 Size : 998 Publisher : 杨锐
【Other resource】 CRC_VHDL DL : 0: 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
Update : 2008-10-13 Size : 205294 Publisher : 刘超
【Other resource】 1024_FFT DL : 0: 1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input / output, with DMA function, the ip xilinx
Update : 2008-10-13 Size : 629675 Publisher : 刘超
【Crack Hack】 xapp270_verilog DL : 0: xilinx公司三重DES加密代码，内部有用于仿真的文件-xilinx companies Triple DES encryption code used for simulating an internal document
Update : 2008-10-13 Size : 13519 Publisher : 王晓涧
【Other resource】 S3Demo DL : 0: 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS / 2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
Update : 2008-10-13 Size : 292348 Publisher : 计算机
【Other resource】 simple_fm_receiver.tar DL : 0: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Update : 2008-10-13 Size : 70152 Publisher : 喻袁洲
【Other】 Peak_Detector_skeleton DL : 0: 这个是Xilinx编程的源码，是Bristol大二时写的．-Xilinx is the programming source code, is sophomore at Bristol writes.
Update : 2008-10-13 Size : 14530 Publisher : Brian
【Other resource】 HowtosimulateIPCore DL : 0: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit -
Update : 2008-10-13 Size : 359836 Publisher : 任学
【Other resource】 FFT_IP DL : 0: Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
Update : 2008-10-13 Size : 419604 Publisher : zxinkai
【Other resource】 yunsuan-verilog DL : 0: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Update : 2008-10-13 Size : 1600570 Publisher : 王越
【Other resource】 trafficLight-verilog DL : 0: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Update : 2008-10-13 Size : 1533527 Publisher : 王越

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