Search - modesim

Search - modesim - List

【VHDL-FPGA-Verilog】 5B6B-codec DL : 1: verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块，信号源模块，编码模块，译码模块，和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, decoding module, and error detection module, and through modesim simulation.
Update : 2024-04-29 Size : 4096 Publisher : 林海全
【matlab】 FFT_TEST DL : 0: FFT 仿真程序结合modesim使用，matlab原码-FFT simulation program with modesim use, matlab original code
Update : 2024-04-29 Size : 1024 Publisher : tangganping
【matlab】 FFT_TEST DL : 0: modesim 的仿真测试文件，Matlab文件，需要自己设置部分参数-modesim simulation test file, Matlab file, need to set some parameters
Update : 2024-04-29 Size : 1024 Publisher : tangganping
【VHDL-FPGA-Verilog】 zhongzhilvbo DL : 0: xilinx ise 与modesim联合验证中值滤波含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
Update : 2024-04-29 Size : 280576 Publisher : bambod
【VHDL-FPGA-Verilog】 FIR DL : 1: 基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
Update : 2024-04-29 Size : 586752 Publisher : zengdeqian
【VHDL-FPGA-Verilog】 modelsim-run-one-step--Error- DL : 0: 用modesim仿真的时候会出现只运行了一步就不动了，显示"# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."的解决方法。-With modesim simulation run only when there will be a step not move, display " #** Error: (vsim-3601) Iteration limit reached at time 0 ps." Solution.
Update : 2024-04-29 Size : 6144 Publisher : dengyaohui
【Other】 SDRAM_Modelsim DL : 0: 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
Update : 2024-04-29 Size : 2521088 Publisher : 刘淇
【Other】 mux8x1 DL : 0: mux 8x1 in verilog simulated in modesim
Update : 2024-04-29 Size : 1024 Publisher : Adnan
【Documents】 ip_modelsim DL : 0: 对于modesim进行IP核仿真的基础知识-For modesim IP core simulation of the basic knowledge
Update : 2024-04-29 Size : 2246656 Publisher : 王春雨
【Embeded-SCM Develop】 UART DL : 0: 使用verilog实现串口通信功能，modesim仿真成功(Using Verilog to achieve serial communication function, modesim simulation success)
Update : 2024-04-29 Size : 2048 Publisher : 农村小伙
【Embeded-SCM Develop】 pwm_ztj_wo(20171127modesim_ok) DL : 0: 用状态机完成pwm的实现，状态完整，思路清晰，设计后用modesim做了验证，并用于电路设计中。(The realization of PWM is completed with a state machine. The state is complete and the train of thought is clear. After the design, it is verified with modesim and used in the design of the circuit.)
Update : 2024-04-29 Size : 119808 Publisher : godlovejie

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