SDRAM controller based on VHDL source code and modesim verification testbench works

SDRAM读写控制Modelsim仿真
.........................\doc
.........................\...\micron_sdram.pdf
.........................\part1
.........................\.....\part1_32
.........................\.....\........\model
.........................\.....\........\.....\mt48lc2m32b2.v
.........................\.....\........\rtl
.........................\.....\........\...\Command.v
.........................\.....\........\...\control_interface.v
.........................\.....\........\...\Params.v
.........................\.....\........\...\sdr_data_path.v
.........................\.....\........\...\sdr_sdram.v
.........................\.....\........\sim
.........................\.....\........\...\Command.v
.........................\.....\........\...\control_interface.v
.........................\.....\........\...\mt48lc2m32b2.v
.........................\.....\........\...\Params.v
.........................\.....\........\...\sd32try.cr.mti
.........................\.....\........\...\sd32try.mpf
.........................\.....\........\...\sdram_test_tb.v
.........................\.....\........\...\sdr_data_path.v
.........................\.....\........\...\sdr_sdram.v
.........................\.....\........\...\sdtry.cr.mti
.........................\.....\........\...\vsim.wlf
.........................\.....\........\...\wave.do
.........................\.....\........\...\work
.........................\.....\........\...\....\command
.........................\.....\........\...\....\.......\verilog.asm
.........................\.....\........\...\....\.......\_primary.dat
.........................\.....\........\...\....\.......\_primary.vhd
.........................\.....\........\...\....\control_interface
.........................\.....\........\...\....\.................\verilog.asm
.........................\.....\........\...\....\.................\_primary.dat
.........................\.....\........\...\....\.................\_primary.vhd
.........................\.....\........\...\....\mt48lc2m32b2
.........................\.....\........\...\....\............\verilog.asm
.........................\.....\........\...\....\............\_primary.dat
.........................\.....\........\...\....\............\_primary.vhd
.........................\.....\........\...\....\sdram_test_tb
.........................\.....\........\...\....\.............\verilog.asm
.........................\.....\........\...\....\.............\_primary.dat
.........................\.....\........\...\....\.............\_primary.vhd
.........................\.....\........\...\....\sdr_data_path
.........................\.....\........\...\....\.............\verilog.asm
.........................\.....\........\...\....\.............\_primary.dat
.........................\.....\........\...\....\.............\_primary.vhd
.........................\.....\........\...\....\sdr_sdram
.........................\.....\........\...\....\.........\verilog.asm
.........................\.....\........\...\....\.........\_primary.dat
.........................\.....\........\...\....\.........\_primary.vhd
.........................\.....\........\...\....\_info
.........................\.....\........\test_bench
.........................\.....\........\..........\sdram_test_tb.v
.........................\.....\........\wave
.........................\.....\........\....\32wave.bmp
.........................\.....\part2_16
.........................\.....\........\model
.........................\.....\........\.....\mt48lc8m16a2.v
.........................\.....\........\rtl
.........................\.....\........\...\Command.v
.........................\.....\........\...\control_interface.v
.........................\.....\........\...\Params.v
.........................\.....\........\...\sdr_data_path.v
.........................\.....\........\...\sdr_sdram.v
.........................\.....\........\sim
.........................\.....\........\...\Command.v
.........................\.....\........\...\control_interface.v
.............

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