Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared

FIR\COFFICIENT.dat
...\FIR滤波器说明.pdf
...\quantization.m
...\scr\fir_filter.asv
...\...\fir_filter.v
...\...\signal_gen0.v
...\...\tb_fir_filter.v
...\.im\out_data.dat
...\...\signal_1m.dat
...\...\signal_1m.dat.bak
...\...\signal_data.dat
...\...\vsim.wlf
...\...\work\fir_filter\verilog.asm
...\...\....\..........\verilog.rw
...\...\....\..........\_primary.dat
...\...\....\..........\_primary.dbs
...\...\....\..........\_primary.vhd
...\...\....\signal_gen0\verilog.asm
...\...\....\...........\verilog.rw
...\...\....\...........\_primary.dat
...\...\....\...........\_primary.dbs
...\...\....\...........\_primary.vhd
...\...\....\tb_fir_filter\verilog.asm
...\...\....\.............\verilog.rw
...\...\....\.............\_primary.dat
...\...\....\.............\_primary.dbs
...\...\....\.............\_primary.vhd
...\...\....\_info
...\...\....\.temp\vlog4gf2c2
...\...\....\.....\vlog4gk2cb
...\...\....\.....\vlogdj40z3
...\...\....\.....\vloghw15yk
...\...\....\.....\vlogm8na6t
...\...\....\.....\vlogv2m9mn
...\...\....\_vmake
...\...\work.cr.mti
...\...\work.mpf
...\sin_1MHz_gen.m
...\..m\work\fir_filter
...\...\....\signal_gen0
...\...\....\tb_fir_filter
...\...\....\_temp
...\...\work
...\scr
...\sim
FIR

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