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【VHDL-FPGA-Verilog】基于FPGA的李沙育图形发生器 DL : 0: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Update : 2024-05-04 Size : 791552 Publisher : 孔玉
【Other】足球1 DL : 0: 3d max 作业这是一个简单的作业3d max 作业3d max 作业-3d max operation is a simple operation 3d max operations 3d max operations
Update : 2024-05-04 Size : 17408 Publisher : leo
【Other】 200211001401 DL : 0: 3d max 作业这是用3D MAX 做的一个沙发还不错-This is done using the 3D MAX also a good sofa
Update : 2024-05-04 Size : 64512 Publisher : leo
【Books】 fpga 和 cpld入门教程 DL : 0: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA/CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Update : 2024-05-04 Size : 4328448 Publisher : 小易
【VHDL-FPGA-Verilog】 maxshiyan DL : 0: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Update : 2024-05-04 Size : 865280 Publisher : 田晶昌
【OpenGL program】 pzr DL : 0: 在OpengGL中实现3ds max中的Pan, zoom in, zoom out, arc rotate功能。-OpengGL in achieving the 3ds max Pan, zoom in, zoom out, rotate function arc.
Update : 2024-05-04 Size : 263168 Publisher : 熊有益
【Graph program】 maxfilt2 DL : 0: 图象处理的matlab程序，Two-dimensional max filter，希望有用-the Matlab image processing procedures, Two-dimensional max filter, useful
Update : 2024-05-04 Size : 1024 Publisher : yuhanzhou
【GUI Develop】 PhysX_2.4.0_SystemSoftware DL : 0: PhysX是一个显卡图象处理软件，AGEIA为3ds max开发的physX插件可以使3ds max用户创建精细的物理模型并且在不脱离3ds max环境的情况下测试它们。-PhysX is a graphics image-processing software AGEIA for 3ds max physX development of the plug-in enables users to create 3ds max fine of Physics no model in 3ds max out the circumstances under testing.
Update : 2024-05-04 Size : 6409216 Publisher : jkfd
【3D Graphic】 50842922D DL : 0: 3ds max 入门学习教程，希望可以与大家交流交流-learning guide, we hope to share with the exchange
Update : 2024-05-04 Size : 9416704 Publisher : ss
【GUI Develop】 MAX_II_board_schematics.pdf DL : 0: MAXII开发板原理图． Revision Index & Table of Contents MAX II and Pereipherals PCI USB and Power Supplies Prototyping Area-MAXII development board schematics. Revision Index
Update : 2024-05-04 Size : 240640 Publisher : 赵天
【VHDL-FPGA-Verilog】 MAX_II_board_schematics DL : 0: Altera MAX II 开发板原理图-Altera's MAX II development board schematics
Update : 2024-05-04 Size : 241664 Publisher : 周宇
【AI-NN-PR】 bayesfunction DL : 0: bayeserr - Computes the Bayesian risk for optimal classifier. ％ bayescln - Classifier based on Bayes decision rule for Gaussians. ％ bayesnd - Discrim. function, dichotomy, max aposteriori probability. ％ bhattach - Bhattacharya s upper limit of mean class. error. ％ pbayescln - Plots discriminat function of Bayes classifier.-bayeserr- Computes the Bayesian risk for o ptimal classifier. % bayescln- Classifier bas ed on Bayesian decision rule for Gaussians. Bayes% nd- Discrim. function, dichotomy. max aposteriori probability. % bhattach- Bhat tacharya s upper limit of mean class. error. pb% ayescln- Plots discriminat function of Bayes c lassifier.
Update : 2024-05-04 Size : 5120 Publisher : 孟庆
【matlab】 Turbocode DL : 0: 包括turbo码编译码程序，译码算法包括sova及max-log-map算法，并有完整链路验证其性能。-including turbo coding- decoding procedures, SOVA including decoding algorithm and max-log-map algorithm, and link integrity test its performance.
Update : 2024-05-04 Size : 13312 Publisher : tanbo
【OpenGL program】 manyou DL : 0: 实现了3DS Max文件的导入,并且实现了人机交互-3DS Max realized the import documents, and the realization of human-computer interaction
Update : 2024-05-04 Size : 2990080 Publisher : cbzeng
【Other】 VHDL-FPGA-clock DL : 1: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Update : 2024-05-04 Size : 269312 Publisher : 王越
【OpenGL program】 maxLOADER DL : 0: 可以在OPENGL中打开３ｄｓ　ｍａｘ导出的.３ｄｓ文件的小程序-in OpenGL open 3ds max derived .3 ds small document procedures
Update : 2024-05-04 Size : 108544 Publisher : 孙文
【VHDL-FPGA-Verilog】 shuzizhong05 DL : 0: MAX+plus II 9.23 Baseline-MAX plus Baseline II 9.23
Update : 2024-05-04 Size : 258048 Publisher : 冬海
【Graph program】 3Dsmaxcap DL : 0: 3Ds max多边形建模实例茶杯模型，比较简单得一个例子，看看就会！-Application of 3Ds max polygon modeling examples cup model, in a simple example, look at will!
Update : 2024-05-04 Size : 87040 Publisher : 孙
【Graph program】 3Dsmaxyagao DL : 0: 3Ds max多边形建模实例牙膏模型，很简单的例子，看看就会的！-Application of 3Ds max polygon modeling examples toothpaste model, a very simple example, will see!
Update : 2024-05-04 Size : 1293312 Publisher : 孙
【VHDL-FPGA-Verilog】 DigitalClockVHDL DL : 0: 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
Update : 2024-05-04 Size : 83968 Publisher : wangyiran

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