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【Other resource】 ram DL : 0: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Update : 2008-10-13 Size : 2661 Publisher : nick
【Compress-Decompress algrithms】 fifo DL : 0: FIFO电路(first in，first out)，内部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次读出已经写入的数据。因为不存在Address输入，所以请自行设计内藏的读写指针。由FIFO电路输出的EF信号(表示RAM内部的数据为空)和FF信号(表示RAM内部的数据为满)来表示RAM内部的状态，并且控制FIFO的输入信号WEN(写使能)和REN(读使能)。以及为了更好得控制FIFO电路，AEF(表示RAM内部的数据即将空)信号也同时输出。
Update : 2008-10-13 Size : 1376 Publisher : 史先生
【Other resource】 fifo DL : 0: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。
Update : 2008-10-13 Size : 1105 Publisher : shili
【VHDL-FPGA-Verilog】 FIFO_BEFORE DL : 0: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Update : 2024-05-02 Size : 211968 Publisher : eva
【VHDL-FPGA-Verilog】 my_fifo_vhdl DL : 0: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Update : 2024-05-02 Size : 19456 Publisher : 朱效志
【VHDL-FPGA-Verilog】 Synthesizable_FIFO_verilog DL : 0: Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
Update : 2024-05-02 Size : 16384 Publisher : lianlianmao
【VHDL-FPGA-Verilog】 Verilog_FIFO_ram DL : 0: 一个可以综合的Verilog 写的FIFO存储器，word格式-An integrated Verilog wrote FIFO memory, word format
Update : 2024-05-02 Size : 19456 Publisher : hjx
【Embeded-SCM Develop】 fifov1 DL : 0: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、与写时钟同步的写有效（wren）和写数据（wr_data）、与读时钟同步的读有效（rden）和读数据（rd_data）为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Update : 2024-05-02 Size : 378880 Publisher : lsg
【VHDL-FPGA-Verilog】 VHDL-ram_fifo DL : 0: VHDL的ram和fifo model code 包含众多的厂家-VHDL the ram and fifo model code contains a large number of manufacturers
Update : 2024-05-02 Size : 1678336 Publisher : SL
【VHDL-FPGA-Verilog】 an_dcfifo_top_restored DL : 0: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Update : 2024-05-02 Size : 928768 Publisher : alison
【VHDL-FPGA-Verilog】 13 DL : 0: para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
Update : 2024-05-02 Size : 3072 Publisher : libing
【VHDL-FPGA-Verilog】 ASYNCFIFOXPXMOD DL : 0: 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
Update : 2024-05-02 Size : 5120 Publisher : xupeixin
【Embeded-SCM Develop】 VHDL DL : 0: 常见的输入输出及存储器件（ram及fifo）vhdl实现-The vhdl source codes of ram,fifo.
Update : 2024-05-02 Size : 22528 Publisher : xugx
【OS Develop】 program DL : 0: 设计实现4bit FIFO, 数据深度为8，产生满，空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Update : 2024-05-02 Size : 3072 Publisher : shao
【VHDL-FPGA-Verilog】 FPGA_Design_Guide_Chapter1_Westor DL : 0: Update : 2024-05-02 Size : 2136064 Publisher : 陈枫
【VHDL-FPGA-Verilog】 mem_ctrl_latest.tar DL : 0: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Update : 2024-05-02 Size : 331776 Publisher : zhangsan
【Windows Develop】 fifo_design DL : 0: 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
Update : 2024-05-02 Size : 2048 Publisher : 孟霑
【VHDL-FPGA-Verilog】 FIFO DL : 0: 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
Update : 2024-05-02 Size : 183296 Publisher : luosheng
【VHDL-FPGA-Verilog】 ram_fifo_ram DL : 0: 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
Update : 2024-05-02 Size : 8185856 Publisher : 袁官福
【VHDL-FPGA-Verilog】 Synchronous FIFO DL : 0: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate)
Update : 2024-05-02 Size : 264192 Publisher : 渔火

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