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【SCM】 ceshi DL : 0: keil编写，本工程基于CYPRESS的固件程序框架，程序中设置了4个FIFO端点，可实现批量端点间和外部RAM环路测试-keil preparation, the project CYPRESS firmware based framework, the program set up four FIFO endpoint, can be realized between the ends and external RAM volume loop testing
Update : 2024-05-02 Size : 78848 Publisher : liu Jeams
【SCM】 uart DL : 0: Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup for various different mode as required by your application. In this tutorial I will show you how to configure the USART in a most common configuration and simply send and receive data. Later on I will give you my library of USART that can further ease you work. It will be little complicated (but more useful) as it will have a FIFO buffer and will use interrupt to buffer incoming data so that you are free to anything in your main() code and read the data only when you need. All data is stored into a nice FIFO(first in first out queue) in the RAM by the ISR.
Update : 2024-05-02 Size : 1024 Publisher : sstefan
【SCM】 Bulkloop DL : 0: 端口环路测试本工程基于CYPRESS的固件程序框架，程序中设置了4个FIFO端点 2个块输出端点：EP2OUT、EP4OUT 2个块输入端点：EP6IN、EP8IN 程序执行时，往EP2OUT/EP4OUT填充数据后将立即通过自动指针传送送到EP6IN/EP8IN端点（未经过外部RAM），来进行批量端点环路测试。打开工程文件加下的cybulk块传输软件，选择对应端点通道（如：OUT:0X02,IN:0X86 ）设置传输数据大小和传送的内容后，点击右边的START按钮便开始端点间的批量传输，SUCCESSFUL框中将显示成功传输的数据量。可通过CyConsole工具软件来验证该例子注意：由于端点均设置成大小512字节的双缓冲结构，往输出端点发送2K(4个512字节)时将填满通道中的空间，再次发送时将出现传送失败。同理，从充满数据的数据管道中读取2K(4个512字节)的数据后，再次进行读取也将出现操作失败。 -CYPRESS
Update : 2024-05-02 Size : 76800 Publisher : 冒险岛
【VHDL-FPGA-Verilog】 versatile_fifo_latest.tar DL : 0: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。-versatile_fifo
Update : 2024-05-02 Size : 1302528 Publisher : 陈亮
【VHDL-FPGA-Verilog】 memory_cores DL : 0: 通用ram源码包，包括双口ram，单口ram，fifo等-general ram source package，include dual port ram，single port ram，fifo，etc.
Update : 2024-05-02 Size : 36864 Publisher : 东
【VHDL-FPGA-Verilog】 asyncfifo DL : 0: 异步fifo，使用双端口RAM作为memory-asynchronous fifo
Update : 2024-05-02 Size : 2048 Publisher : jason
【VHDL-FPGA-Verilog】 BlockRam DL : 0: 块状ram使用实例，实现深度和宽度可调的FIFO，buffer。-The block ram instance, depth and width adjustable FIFO, buffer.
Update : 2024-05-02 Size : 2963456 Publisher : zwl6600233
【VHDL-FPGA-Verilog】 vhdl-Language-routine-highlights DL : 0: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Update : 2024-05-02 Size : 291840 Publisher : shujian
【VHDL-FPGA-Verilog】 VHDL-memory DL : 0: 存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
Update : 2024-05-02 Size : 33792 Publisher : zmz
【VHDL-FPGA-Verilog】 asyn_fifo DL : 0: 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write).
Update : 2024-05-02 Size : 650240 Publisher : jodyql
【VHDL-FPGA-Verilog】 Dual_ram_verilog_CODE DL : 0: 写了FIFO中要用到的双口RAM的模块,FIFO中的RAM只用于读数据,输出数据,用写时针采集信号,读时针那一端不用读时针来采样.-Written to use the FIFO dual port RAM module, FIFO in the RAM is only used to read data, output data, the clock signal acquisition with write and read without reading that end of the hour to hour sampling.
Update : 2024-05-02 Size : 1024 Publisher : dagegegoni
【VHDL-FPGA-Verilog】 HWL_ASYNC_FIFO_DRAM_BA DL : 0: asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
Update : 2024-05-02 Size : 2048 Publisher : D
【VHDL-FPGA-Verilog】 fifo_mem DL : 0: 同步FIFO，IP核生成ram，已验证可用。-Synchronous FIFO, IP core generation ram, verified available.
Update : 2024-05-02 Size : 1024 Publisher : Devin
【VHDL-FPGA-Verilog】 VHDL_RAM_FIFO_ROM DL : 0: VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer
Update : 2024-05-02 Size : 9634816 Publisher : 胡小军
【VHDL-FPGA-Verilog】 syncfifo DL : 0: 一个简单的基于single port ram 的同步fifo。只能支持只写或只读。-A simple single port ram based on the synchronization fifo. Can only support write-only or read-only.
Update : 2024-05-02 Size : 1024 Publisher : 刘宇洋
【VHDL-FPGA-Verilog】 pg058-blk-mem-gen DL : 0: blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)
Update : 2024-05-02 Size : 1636352 Publisher : CrazyICer
【Other】 SH6883 DL : 0: The SH6883 is designed for high performance Low-speed USB devices. It contains an 8051 micro-controller, Low-Speed USB SIE, Transceiver and data FIFO, build-in 3.3V regulator, on-chip 8K bytes Mask ROM and internal 256 bytes data RAM, Time capture circuit, Base timer, programmable Watch-dog timer and Wake-up timer, 37 Selectable GPIO (on 48-pin LQFP package), support multiple type LED driving capability for different application, build-in internal 32KHz oscillator, POR and LVR circuit saving your external components cost
Update : 2018-08-11 Size : 2154879 Publisher : simoon
【VHDL-FPGA-Verilog】 verilog实例 [43项] DL : 0: 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
Update : 2024-05-02 Size : 190464 Publisher : hayto

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