Search - decimation

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【matlab】 CIC DL : 0: matlab实现一个decimation为4的CIC滤波器-matlab implementation of a decimation filter for 4 of the CIC
Update : 2024-04-28 Size : 1024 Publisher : morang
【VHDL-FPGA-Verilog】 CIC_deci4 DL : 0: cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证-CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
Update : 2024-04-28 Size : 31744 Publisher : mimidabuda
【VHDL-FPGA-Verilog】 cic_dec_8_three DL : 0: 8位三级CIC抽取滤波器，VHDL语言版~-8 three-CIC decimation filter
Update : 2024-04-28 Size : 1024 Publisher : 文强
【VHDL-FPGA-Verilog】 CIC_DEC DL : 0: CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
Update : 2024-04-28 Size : 1024 Publisher : 42200306
【VHDL-FPGA-Verilog】 CIC_DEC_3 DL : 0: CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
Update : 2024-04-28 Size : 1024 Publisher : 42200306
【VHDL-FPGA-Verilog】 CIC_DEC_6 DL : 0: CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
Update : 2024-04-28 Size : 1024 Publisher : 42200306
【SCM】 Enhancing_ADC_resolution_by_oversampling DL : 0: 使用过采样的方法提高AVR的模数转换器的精度 "过采样和抽取"的方法，以及应用该方法而非外部的模数转换器达到提高精度的目的时所应满足的条件。-This Application Note explains the method called "Oversampling and Decimation" and which conditions need to be fulfilled to make this method work properly to get achieve higher resolution without using an external ADC.
Update : 2024-04-28 Size : 253952 Publisher : ECN
【Other】 cicDecimate DL : 0: CIC filter decimator for Matlab
Update : 2024-04-28 Size : 2048 Publisher : Harry Li
【DSP program】 fft1drad2cmpx_121900 DL : 0: ADI 的 ADSP_BF533 FFT程序-This file contains the code for the implementation of FFT. The Algorithm used is Decimation in Time. For the optimization point of view, the whole computation of butterfly signal flow has beeen divided in three parts. The first part, the middle part and the last part. In the first part, the Stage 1 and Stage 2 of the butterfly structure are implemented. In the 2nd part the general butterfly computation is done, which corresponds to the middle stages of butterfly. In the last part the last stage of the buttrfly structure is implemented, where mainly the loop overheads are saved.
Update : 2024-04-28 Size : 76800 Publisher : 王君
【matlab】 FFT DL : 0: matlab program to fing FFT of given sequence using decimation in time and decimation in frequency algorithms
Update : 2024-04-28 Size : 1024 Publisher : Deepthi
【Communication-Mobile】 chouqu DL : 0: 抽取倍数是4倍的多相抽取滤波器，用于降低接收信号的速率。-multi_phase decimation filter
Update : 2024-04-28 Size : 3264512 Publisher : 莱茵夏
【Software Engineering】 compensationfilterdesign DL : 0: 带余弦预滤波和补偿滤波的抽取滤波器　设计方案-Pre-filtering with a cosine decimation filter and compensation filter design
Update : 2024-04-28 Size : 368640 Publisher : 王楚宏
【Software Engineering】 FPGAfir DL : 0: FPGA实现FIR抽取滤波器的设计　采用基于分布式思想的方法来设计FIR滤波器。-FPGA realization of FIR decimation filter design ideas based on a distributed approach to design FIR filters.
Update : 2024-04-28 Size : 164864 Publisher : 王楚宏
【Software Engineering】 lvbofangfa DL : 0: 针对全数字软件接收机中抽取滤波器的设计,提出了一种适合在FPGA内实现的单级积分清洗的滤波器结构,这种结构解决了传统积分梳妆滤波器中可能出现的积分器溢出问题,同时还可进行非整数倍的抽取变换.给出了一种无乘法半带滤波器的IIR实现结构,并对该滤波器性能进行了仿真,结果表明在输出过采样率大于4时基本不会影响系统误码性能.-Software for all-digital receiver decimation filter design, presents a suitable FPGA integration within the single-stage cleaning filter structure that points to solve the traditional dressing filters that may arise integrator overflow problem , but can also carry out the extraction of non-integer transform. gives a multiplication-free realization of IIR half-band filter structure and performance of the filter simulation results show that the output sampling rate is greater than 4:00 over the basic will not affect the system BER performance.
Update : 2024-04-28 Size : 196608 Publisher : 王楚宏
【Software Engineering】 DDCFPGA DL : 0: 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T receiver machine multi-rate DDC module, and the simulation in the FPGA implementation. Numerical oscillation in the complex mixer module, based on the input signals of different bandwidths (6M/8MHz) choose a different group of complete decimation filter extracted factor 3 or 4 of the multi-rate processing tasks, using two half-band filter (HBF) cascade to complete four times decimation filter, single-stage Chennai Nyquist filter to complete three times the decimation filtering.
Update : 2024-04-28 Size : 309248 Publisher : 王楚宏
【Streaming Mpeg4】 123456789 DL : 0: 以一个多相抽取滤波器为例，介绍滤波器组的编码方式，包括主程序模块和子程序模块-With a polyphase decimation filter, for example, introduced the filter encoding methods, including the main program modules and subroutines Module
Update : 2024-04-28 Size : 1024 Publisher : AndyLee
【Books】 fir DL : 0: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Update : 2024-04-28 Size : 201728 Publisher : jiang
【Other】 ImageDecimationandInterpolation DL : 0: Image Decimation and Interpolation
Update : 2024-04-28 Size : 57344 Publisher : firdevs
【Algorithm】 16_points_DIT_FFT_MATLAB DL : 0: 基于时域抽取的1024点FFT函数。适合用于演示算法计算过程，既教学。可以扩展成2次幂点数的FFT计算。开发环境MATLAB。-1024-point Decimation-in-time FFT function. Algorithm suitable for presentation process, both the teaching. Can be expanded into a power of two points of the FFT calculation. Development environment, MATLAB.
Update : 2024-04-28 Size : 1024 Publisher : 南杰胤
【VHDL-FPGA-Verilog】 fir_dec3 DL : 0: FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
Update : 2024-04-28 Size : 2048 Publisher : 王刚

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