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【Other】 add4bit DL : 0: 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
Update : 2024-05-05 Size : 813056 Publisher : 祁才君
【Software Engineering】 FPGA DL : 0: 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processing in the most extensive one of the implementation of components, the paper design of the three types of FPGA-based digital multiplier. Shift sum are noise multiplication, adder tree multiplier and the sum of a displacement hybrid adder tree multiplier noise. Through the simulation of three options to building a comprehensive comparison of the speed and size that the multiplier is one of the best hybrid design
Update : 2024-05-05 Size : 147456 Publisher : 南才北往
【Other Embeded program】 systemc DL : 0: Systemc实现一个加法器，一个乘法器，一个十选一器，并在testbench内检测其正确性。适用于systemc入门。-Using Systemc for the realization of a adder, a multiplier, a decimator, and within a testbench for their functionalities . Designed for Systemc or C++ beginner .
Update : 2024-05-05 Size : 3072 Publisher : 安丽华
【VHDL-FPGA-Verilog】 HalfAdderDesign DL : 0: Half Adder Using Verilog
Update : 2024-05-05 Size : 8192 Publisher : hallowen
【Windows Develop】 fpadd DL : 0: Floating point adder
Update : 2024-05-05 Size : 10240 Publisher : Shani Kumar Goutam
【VHDL-FPGA-Verilog】 adder DL : 0: This the adder VHDL code, it contains input and output fild, also simulate file-adder
Update : 2024-05-05 Size : 5120 Publisher : hongwan
【Embeded-SCM Develop】 lab7 DL : 0: 在這個實習當中，我們學習利用 Hierarchical VHDL code 的方式，來實現一個n-bit 的ripple-carry adder，並學習使用package。-In this practice among the profit we can learn to use Hierarchical VHDL code the way to achieve an n-bit future of the ripple-carry adder, and learn to use package.
Update : 2024-05-05 Size : 82944 Publisher : 徐小華
【VHDL-FPGA-Verilog】 adder DL : 0: 用vhdl实现加法器的功能，程序简介高效，移植性强-Vhdl adder with the realization of the function, procedures for efficient, portable and strong
Update : 2024-05-05 Size : 1024 Publisher : keyes wang
【VHDL-FPGA-Verilog】 four_adder DL : 0: 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
Update : 2024-05-05 Size : 149504 Publisher : 安博
【Algorithm】 adder DL : 0: 加法器，简单的加法计算器程序，用vb语言实现-Adder, a simple addition calculator program using vb language implementation
Update : 2024-05-05 Size : 5120 Publisher : 邹诗
【VHDL-FPGA-Verilog】 addersandsubtractors DL : 0: this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Update : 2024-05-05 Size : 65536 Publisher : jatab
【VHDL-FPGA-Verilog】 adder DL : 0: vhdl adder with two input 4-bit and output of 4 bits and carry
Update : 2024-05-05 Size : 1024 Publisher : querias
【VHDL-FPGA-Verilog】 ADDER DL : 0: VHDL语言的带控制端口的加法器，实现加法运算。-VHDL language, with a control port of the adder to achieve addition operation.
Update : 2024-05-05 Size : 22528 Publisher : piikee
【VHDL-FPGA-Verilog】 adder DL : 0: 加法器程式設計,這是利用verilog寫的-adder
Update : 2024-05-05 Size : 10240 Publisher : 鍾潤宏
【VHDL-FPGA-Verilog】 RA DL : 0: ripple adder 程式撰寫,此利用verilog撰寫-ripple adder
Update : 2024-05-05 Size : 2048 Publisher : 鍾潤宏
【Embeded Linux】 83390078DDS DL : 0: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Update : 2024-05-05 Size : 44032 Publisher : 394177191
【VHDL-FPGA-Verilog】 flowvhdl DL : 0: 16 bit adder source code.
Update : 2024-05-05 Size : 128000 Publisher : midhunraj
【Software Engineering】 cla DL : 0: Carry Look ahead adder
Update : 2024-05-05 Size : 2048 Publisher : Senthil Kumar
【File Format】 bitbcdadder DL : 0: bcd adder implemented in three models of vhdl
Update : 2024-05-05 Size : 59392 Publisher : sathishkumar
【File Format】 Carrylookaheadadder DL : 0: carry look ahead adder implented in 3 models of vhdl-carry look ahead adder implented in 3 models of vhdl
Update : 2024-05-05 Size : 47104 Publisher : sathishkumar

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