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【VHDL-FPGA-Verilog】 voterandcounter DL : 0: 用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
Update : 2024-05-05 Size : 2048 Publisher : 韩笑
【VHDL-FPGA-Verilog】 adder DL : 0: cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
Update : 2024-05-05 Size : 2048 Publisher : 陈臣
【source in ebook】 f_adder DL : 0: 全加器，全加器-Full-adder, full adder, full adder
Update : 2024-05-05 Size : 102400 Publisher : Betty
【Other】 adder DL : 0: 多位数加法多位数加法 -More than the median more than the median adder adder adder more than the median
Update : 2024-05-05 Size : 160768 Publisher : fabio
【VHDL-FPGA-Verilog】 cla16 DL : 0: verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of the aggregate output carryout// binary input [15:0] A_in// input Ainput [15:0] B_in// input Binput carryin// article C0-level binary
Update : 2024-05-05 Size : 2048 Publisher : 沙嗲
【VHDL-FPGA-Verilog】 adder4 DL : 0: 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
Update : 2024-05-05 Size : 1024 Publisher : olive
【VHDL-FPGA-Verilog】 seven DL : 0: 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full adder mapping method in order to achieve a vote of seven functions, with the network on any other A seven-member voting machine source code must not identical.
Update : 2024-05-05 Size : 84992 Publisher : daisichong
【VHDL-FPGA-Verilog】 adder DL : 0: 用VHDL语言实现半加器。已经通过编译和仿真-Implementation using VHDL language half adder. Has passed the compiler and simulation
Update : 2024-05-05 Size : 141312 Publisher : 孟明川
【Windows Develop】 fulladder DL : 0: full adder. dai jinwei de liangwei quan jiaqi-fulladder
Update : 2024-05-05 Size : 1024 Publisher : aaaaaaa7
【VHDL-FPGA-Verilog】 add(FLP) DL : 0: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Update : 2024-05-05 Size : 10240 Publisher : TTJ
【Windows Develop】 a_serial_adder DL : 0: 一位串行加法器，是用MAXPLUSII实现VHDL程序的编程-A serial adder is used MAXPLUSII programming VHDL implementation
Update : 2024-05-05 Size : 47104 Publisher : da
【Other】 adder DL : 0: this code written in systemc language and it is a wewest language that important to simulate the system
Update : 2024-05-05 Size : 1024 Publisher : zooz
【Other Embeded program】 fulladder DL : 0: 一个全加器的systemc代码，包括模块的定义以及测试平台-A source code about full adder using systemc language , including the definition of modules as well as the test platform
Update : 2024-05-05 Size : 2048 Publisher : 刘飞阳
【VHDL-FPGA-Verilog】 Mars_EP1C6F_Fundermental_demo(Verilog) DL : 0: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Update : 2024-05-05 Size : 1244160 Publisher : chenlu
【Linux-Unix】 fpadd DL : 0: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Update : 2024-05-05 Size : 12288 Publisher : 孟军
【VHDL-FPGA-Verilog】 adder DL : 0: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Update : 2024-05-05 Size : 1024 Publisher : surya
【VHDL-FPGA-Verilog】 Adder DL : 0: 实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl
Update : 2024-05-05 Size : 105472 Publisher : maxpayne
【VHDL-FPGA-Verilog】 adder DL : 0: verilog for full_adder
Update : 2024-05-05 Size : 1024 Publisher : max
【VHDL-FPGA-Verilog】 add DL : 0: 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
Update : 2024-05-05 Size : 13312 Publisher : yigezi
【source in ebook】 adder DL : 0: 全加器，用fpga语言编写的，可实现数字电路技术中的全加器的功能，符合逻辑原理图。-adder
Update : 2024-05-05 Size : 3072 Publisher : xiaopeng

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