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【VHDL-FPGA-Verilog】 primetime DL : 0: 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
Update : 2024-05-19 Size : 52224 Publisher : 张国梁
【Other】 VhdlLanguageReferenceMmanualIEEE1076 DL : 0: vhdl language reference manual IEEE1076(2004.10)-VHDL language reference manual IEEE1076 (2004.10)
Update : 2024-05-19 Size : 1301504 Publisher : 谭贤豪
【VHDL-FPGA-Verilog】 wodevhdl DL : 0: vhdl练习实例。在maxplus2中编写，编译通过，正确。-VHDL practice examples. In maxplus2 prepare, compile and correct.
Update : 2024-05-19 Size : 65536 Publisher : 梦雨
【VHDL-FPGA-Verilog】 Lab_ISE_Led DL : 0: vhdl实例教程，其中的例子适合新手演示使用，肯定会有帮助的。-VHDL example tutorial, an example of the use for novice demo, it will certainly help.
Update : 2024-05-19 Size : 779264 Publisher : ghjghj
【VHDL-FPGA-Verilog】 wom_kg DL : 0: 系统时钟的VHDL电路，适合有一定经验的编程人员，希望能对你们有帮助。-VHDL system clock circuit suitable for a certain programming experience, you want to help.
Update : 2024-05-19 Size : 24576 Publisher : ghjghj
【VHDL-FPGA-Verilog】 8bitsine DL : 0: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Update : 2024-05-19 Size : 5120 Publisher : 王刚
【VHDL-FPGA-Verilog】 RISC DL : 0: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Update : 2024-05-19 Size : 128000 Publisher : 12
【VHDL-FPGA-Verilog】 32fenpinqi DL : 0: 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。多指正，交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
Update : 2024-05-19 Size : 12288 Publisher : 刘彦平
【VHDL-FPGA-Verilog】 44vhdl DL : 0: 44个vhdl实例注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Update : 2024-05-19 Size : 44032 Publisher : 土木文田
【VHDL-FPGA-Verilog】 hiervhdl DL : 0: Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
Update : 2024-05-19 Size : 44032 Publisher : 土木文田
【VHDL-FPGA-Verilog】 clk_divide_3 DL : 0: VHDL语言编写三分频，可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
Update : 2024-05-19 Size : 124928 Publisher : 利津候
【VHDL-FPGA-Verilog】 78_alu_input DL : 0: vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
Update : 2024-05-19 Size : 2048 Publisher : tom
【VHDL-FPGA-Verilog】 ProgramText DL : 0: we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.-we will use the cables Spartan3 FPGA design to a specified counter using the VHDL language.
Update : 2024-05-19 Size : 12288 Publisher : fei
【VHDL-FPGA-Verilog】 hdb3_VHDL DL : 0: hdb3 using language VHDL-Indoor using VHDL language
Update : 2024-05-19 Size : 54272 Publisher : 王锋
【VHDL-FPGA-Verilog】 2Dfft DL : 0: VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.-VHDL design procedures on 2DFFT u scinode1
Update : 2024-05-19 Size : 783360 Publisher : 李成
【Documents】 ripple-lookahead-carryselect-adder DL : 0: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Update : 2024-05-19 Size : 15360 Publisher : 李成
【VHDL-FPGA-Verilog】 ceshixiangliang DL : 0: vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples--- corresponding Adder test vector (test bench). Txt
Update : 2024-05-19 Size : 11264 Publisher : 陈丽
【Other】 full_add DL : 0: 一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.
Update : 2024-05-19 Size : 123904 Publisher : 陈晓岚
【VHDL-FPGA-Verilog】 12864lcd_vhdl DL : 0: 12864图形点阵液晶驱动vhdl程序，用ise综合-12864 graphics dot-matrix LCD driver VHDL program, and ideally integrated
Update : 2024-05-19 Size : 9423872 Publisher : 赵晗
【VHDL-FPGA-Verilog】 vgaCode DL : 0: VGA动画显示，用VHDL编程，用ise开发-VGA animation, VHDL programming, ideally with development
Update : 2024-05-19 Size : 7168 Publisher : 赵晗

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