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【VHDL-FPGA-Verilog】 CH2CH1VHDL 数字电路参考书所有程序2 DL : 0: CH2 VHDL 数字电路参考书所有程序2-CH2 VHDL digital circuit two reference books all procedures
Update : 2024-05-19 Size : 134144 Publisher : 胡计划
【ISAPI-IE】 subr DL : 0: VHDL 8位无符号除法器试验报告计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。其实现方法是，将除法器分为两个状态：等待状态与运算状态。开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Update : 2024-05-19 Size : 82944 Publisher : aa
【Other】 ALARM_SET DL : 0: 用VHDL编写的一个闹钟的控制程序，希望大家看了后能喜欢，也可以学学哟！-VHDL prepared an alarm clock control procedures in the hope that everyone will love after reading them, but also can learn yo!
Update : 2024-05-19 Size : 1024 Publisher : lw
【VHDL-FPGA-Verilog】 cpu16 DL : 0: 一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
Update : 2024-05-19 Size : 3072 Publisher : 王林
【EditBox】 enc DL : 0: HDB3编码器使用VHDL编制对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
Update : 2024-05-19 Size : 1024 Publisher : ls
【VHDL-FPGA-Verilog】 msttr DL : 0: msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
Update : 2024-05-19 Size : 4096 Publisher : 王剑
【Other】 AskPsk DL : 0: ask psk 编码调制的vhdl 实现-ask psk coded modulation to achieve the VHDL
Update : 2024-05-19 Size : 72704 Publisher : 王发
【VHDL-FPGA-Verilog】 richic_vga_top DL : 0: 有关 VHDL进行VGA显示的源程序，请大家好好参考-VHDL for the VGA display the source code, please make reference to
Update : 2024-05-19 Size : 27648 Publisher : 111
【VHDL-FPGA-Verilog】分频器VHDL描述 DL : 0: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Update : 2024-05-19 Size : 5120 Publisher : 王力
【Other】 autosale DL : 0: VHDL编写的自动售货机，带找零、退币功能，数字电路课程设计！内附常态图，和dofile波形模拟文件-VHDL prepared by the vending machines, have sought to bring, the coin features, digital circuit design courses! Enclosing normal map and document dofile waveform simulation
Update : 2024-05-19 Size : 3072 Publisher : 张傻
【Other】 trafficlight DL : 1: VHDL编写的交通灯程序，有倒计时功能，数字电路课程设计，内附状态图和dofile波形模拟！-VHDL prepared by the traffic lights procedures, the countdown function, digital circuit design courses, enclosing a state map and dofile waveform simulation!
Update : 2024-05-19 Size : 4096 Publisher : 张傻
【VHDL-FPGA-Verilog】 core51_VHDL DL : 0: VHDL写的51单片机内核，实现51的全部工能，学习开发FPGA的参考资料。-VHDL wrote 51 microcontroller core, the realization of all the 51 workers may learn FPGA development of reference materials.
Update : 2024-05-19 Size : 95232 Publisher : 杨标
【Embeded-SCM Develop】 memoire_alphabet DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Update : 2024-05-19 Size : 1024 Publisher : 秦拣俭
【VHDL-FPGA-Verilog】 baud DL : 0: vhdl 很好用于串行通信. 三个模快,发生时钟,发送和接收过程-VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
Update : 2024-05-19 Size : 124928 Publisher : 刘三
【VHDL-FPGA-Verilog】 tcdg.vhdl DL : 0: des vhld 源码　程序完成了DES的编码和解码功能-des vhld source procedures completed DES encoding and decoding
Update : 2024-05-19 Size : 5120 Publisher : 王亮
【VHDL-FPGA-Verilog】 PCI_144 DL : 1: -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144---- Synopsys VHDL Solution using Xilinx XC7000 Library
Update : 2024-05-19 Size : 3072 Publisher : processor
【VHDL-FPGA-Verilog】 control step motor DL : 0: 步进电机控制，控制器,控制电机的VHDL源程序-stepper motor control, controllers, motor control VHDL source
Update : 2024-05-19 Size : 1024 Publisher : 刘
【VHDL-FPGA-Verilog】 dds_vhdl DL : 0: dds的vhdl实现,主要包括正弦波、三角波和锯齿波的产生-dds achieve the VHDL, including sine, triangle wave, and the selection ramp
Update : 2024-05-19 Size : 1024 Publisher : xxx
【EditBox】 S3BOARD-demo DL : 0: vga 程序 demo程序，可以用，线条显示可编程逻辑设计vhdl语言编写-vga procedures demo procedures can be used, the lines show programmable logic design, VHDL language
Update : 2024-05-19 Size : 310272 Publisher : 冯理
【VHDL-FPGA-Verilog】 vhdl_vga_kb DL : 0: VHDL的显示驱动程序，VHDL的PS2键盘驱动程序-VHDL display drivers, VHDL PS2 Keyboard Driver
Update : 2024-05-19 Size : 3072 Publisher : 张明凯

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