Search - FIFO

Search - FIFO - List

【DSP program】 SCI-FIFO DL : 0: TMS20f28335之SCIB模块fifo模式通信-fqfqf vgvrn bsdbsdb bxbx aniahfi jhsufhu fnueu osaoonc
Update : 2024-04-30 Size : 5120 Publisher : 张鹏
【File Format】 FIFO-BRANCE-AND-BOUND DL : 0: IT IS FOR FIFO BRANCE AND BOUND TECHNEQUE
Update : 2024-04-30 Size : 321536 Publisher : nanao
【VHDL-FPGA-Verilog】 FIFO-DOCUMENATATION DL : 0: DOCUMENTATION OF FIFO
Update : 2024-04-30 Size : 868352 Publisher : sree
【VHDL-FPGA-Verilog】 fifo DL : 0: FIFO是通过时钟来确定是同步还是异步的，同步FIFO的读写操作是通用一个时钟来控制的。另一方面。两个不同频率或者不同香味的时钟来控制异步FIFO的读写操作。异步FIFO 跨越时钟域的同步问题-FIFO is determined by the clock is synchronous or asynchronous, synchronous FIFO read and write operations are a common clock control. on the other hand. Two different frequencies or different flavor to control the clock asynchronous FIFO read and write operations. FIFO asynchronous clock domain crossing synchronization issues
Update : 2024-04-30 Size : 3072 Publisher : Isabelle Cheung
【Other】 FIFO DL : 0: FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
Update : 2024-04-30 Size : 67584 Publisher : sam
【ARM-PowerPC-ColdFire-MIPS】 zc706-axi-dma-fifo-master DL : 0: zc706 axi-dma-fifo-master example
Update : 2024-04-30 Size : 31744 Publisher : Yerba
【Industry research】 fifo DL : 0: fifo scheduling program
Update : 2024-04-30 Size : 72704 Publisher : yagami
【VHDL-FPGA-Verilog】 uart DL : 0: 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
Update : 2024-04-30 Size : 145408 Publisher : 陈陈陈啊
【VHDL-FPGA-Verilog】 asyn_fifo DL : 0: 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
Update : 2024-04-30 Size : 1024 Publisher : 叶古
【VHDL-FPGA-Verilog】 syn_fifo DL : 0: 该源码包是同步fifo的Verilog语言模型，主要包括2个部分：同步fifo控制模块、测试文件。(The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.)
Update : 2024-04-30 Size : 1024 Publisher : 叶古
【Windows Develop】 FIFO DL : 0: 最近最少使用页面(FIFO)置换算法，是最简单的页面置换算法。这种算法的基本思想是：当需要淘汰一个页面时，总是选择驻留主存时间最长的页面进行淘汰，即先进入主存的页面先淘汰。其理由是：最早调入主存的页面不再被使用的可能性最大。(Recently, the least use of page (FIFO) replacement algorithm)
Update : 2024-04-30 Size : 1024 Publisher : 白茶
【Other】无FIFO摄像头 IO抓取 DL : 0: 通过i/o口模拟时序抓取ov7670的图像(Through the i / o port simulation time to capture the ov7670 image)
Update : 2024-04-30 Size : 3256320 Publisher : DSP菜鸟
【VHDL-FPGA-Verilog】 uartverilog DL : 0: FPGA利用串口、FIFO实现串口收发数据(FPGA using serial port, FIFO serial transceiver data)
Update : 2024-04-30 Size : 196608 Publisher : mzl127
【Linux-Unix】命名管道：FIFO DL : 0: 命名管道也被称为FIFO文件，它是一种特殊类型的文件，它在文件系统中以文件名的形式存在，但是它的行为却和之前所讲的没有名字的管道（匿名管道）类似。由于Linux中所有的事物都可被视为文件，所以对命名管道的使用也就变得与文件操作非常的统一，也使它的使用非常方便，同时我们也可以像平常的文件名一样在命令中使用。(A named pipe is also known as the FIFO file, it is a special type of document and its file name in the file system to form, but it is the behavior of pipeline and have said before no name (similar to anonymous pipes). Because everything in Linux can be seen as a file, so the use of named pipes becomes uniform and the file operation very well, but also make it very convenient to use, and we can also use the same name as the normal file in the order.)
Update : 2024-04-30 Size : 2048 Publisher : 。。。，，，
【VHDL-FPGA-Verilog】 FIFO_ASY DL : 0: 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
Update : 2024-04-30 Size : 2048 Publisher : 253765952
【VHDL-FPGA-Verilog】 CCD_Array DL : 0: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
Update : 2024-04-30 Size : 3320832 Publisher : muralidh
【VHDL-FPGA-Verilog】带FIFO的ov7670 FPGA应用程序，经测试可用 DL : 0: 这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
Update : 2024-04-30 Size : 1683456 Publisher : jomair
【VHDL-FPGA-Verilog】 syn_dp_fifo.v DL : 0: 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
Update : 2024-04-30 Size : 1024 Publisher : junkaizhan
【VHDL-FPGA-Verilog】 sp6ex19 DL : 0: FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
Update : 2024-04-30 Size : 5181440 Publisher : 没伞的孩子
【SCM】 OV7725 DL : 0: ov7725 彩色摄像头带fifo tft显示(Ov7725 color camera and have fifo .then display it)
Update : 2024-04-30 Size : 3856384 Publisher : 打鸟day

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