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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2017-07-07
- Size : 1kb
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- Author ：叶****
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The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.
Packet file list
(Preview for download)
tb_fifo.v
syn_fifo.v
syn_fifo.v
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