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【Embeded Linux】 FIFO DL : 0: 基于ARM实现FIFO通讯协议，可移植性好，调试通过-ARM-based communication protocol to achieve FIFO, portability, debugging through
Update : 2024-05-17 Size : 327680 Publisher : cyl
【VHDL-FPGA-Verilog】 Synchronous-FIFO DL : 0: FIFO是英文FIRST-IN-FIRST-OUT的缩写，是一种先进先出的数据缓存器，它与普通存储器的区别是没有外部读写地址线，这样使用起来非常方便，但是缺点是只能顺序读写数据，其数据地址由内部读写指针自动加1完成 FIFO的主要功能是基于对双口RAM的读写控制来完成的，根据双口RAM的数据存储状况产生空满信号。双口RAM指的就是能同时对RAM进行读写操作的RAM存储器 -FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT, which is a FIFO data buffer, it is the difference between ordinary memory is no external write address lines, so very convenient to use, but the drawback is that only the order read and write data, the data read by the internal address pointer is automatically incremented by 1 to complete the FIFO main function is based on the dual-port RAM read and write control to complete, resulting in empty status full signal based on data stored in the dual-port RAM. Refers to the dual-port RAM can simultaneously read and write RAM RAM memory
Update : 2024-05-17 Size : 4096 Publisher : 刘东辉
【VHDL-FPGA-Verilog】 FIFO DL : 0: Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit-Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit
Update : 2024-05-17 Size : 3569664 Publisher : Huu Duc
【VHDL-FPGA-Verilog】 fifo DL : 0: 同步fifo，可以进行读写操作，使用rom ip核进行存储数据，可以作为参考。-Synchronous fifo, read and write operations can be performed using the rom ip core for storing data can be used as a reference.
Update : 2024-05-17 Size : 2048 Publisher : 张雯雯
【OS Develop】 FIFO DL : 0: 设计程序模拟FIFO页面置换算法的工作过程。假设内存中分配给每个进程的最小物理块数为m，在进程运行过程中要访问的页面个数为n，页面访问序列为P1, … ,Pn，分别利用不同的页面置换算法调度进程的页面访问序列，给出页面访问序列的置换过程，并计算每种算法缺页次数和缺页率。-The design process of the analog FIFO page replacement algorithm work process. Suppose the minimum number of physical blocks allocated to each process in memory is m, the page number in the process during operation to access to n, page views sequence P1, ..., Pn, each with different page replacement algorithm scheduling process page access sequence permutation process given page access sequences, and each algorithm calculated the number of missing pages and page rate.
Update : 2024-05-17 Size : 27648 Publisher : 江啸澜
【VHDL-FPGA-Verilog】 fifo DL : 0: 异步FIFO的实现，很经典的三段式状态机的写法。-The realization of the asynchronous FIFO, very classic three-step writing state machine.
Update : 2024-05-17 Size : 1024 Publisher : 孙金傲
【VHDL-FPGA-Verilog】 fifo DL : 0: 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
Update : 2024-05-17 Size : 3777536 Publisher : liyi
【VHDL-FPGA-Verilog】 FIFO DL : 0: FPGA TI DSP的EMIF接口的地址总线问题-FPGA FIFO
Update : 2024-05-17 Size : 2849792 Publisher : liuky
【VHDL-FPGA-Verilog】 fifo DL : 0: 使用Verilog实现异步fifo的功能-Use Verilog implementation of asynchronous fifo functionality
Update : 2024-05-17 Size : 1205248 Publisher : Amy_nmw
【VHDL-FPGA-Verilog】 FIFO DL : 0: 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
Update : 2024-05-17 Size : 135168 Publisher : seer
【SCM】 FIFO DL : 0: 环形FIFO, 用于51单片机, 全指针实现, 效率很高-Ring FIFO, for 51 single-chip, all-pointers, high efficiency
Update : 2024-05-17 Size : 4096 Publisher : 孙和庆
【Software Engineering】 FIFO DL : 0: fifo程序代码，程序编写，测试仿真图形，方便，比较实用-fifo code, programming, testing, simulation graphics, convenient and more practical
Update : 2024-05-17 Size : 2048 Publisher : 黎明
【SCM】 FIFO-for-rs232-and-rs485 DL : 0: 用stm32写的一个例子，用到了232和485通讯，模拟了一个fifo,可以直接使用，希望有用-Use stm32 write an example, use 232 and 485, simulates a fifo, can be used directly, the hope that useful
Update : 2024-05-17 Size : 320512 Publisher : 张晶洵
【MPI】 FIFO DL : 0: FIFO读写操作，quartusII VHDL IP FPGA-FIFO VHDL IP FPGA
Update : 2024-05-17 Size : 100352 Publisher : eclipseds5
【GUI Develop】 FIFO DL : 0: 1.登录的账号：yangmingyuan 登录的密码：123456 2.物理块数由用户自己输入大小可以随意选定。 3. 在输入请求的页面时候，请依次输入页面号并且页面号之间要用空格隔开，最后不要有空格等其他非数字字符结束。 4.然后单击输入按钮将页面号输入，弹出确定的对话框单击确定，最后单击开始FIFO按钮开始执行调页算法。在调页过程框中观察具体的调页顺序及调页过程，并且可以观察到缺页数和缺页率的大小。 5.最后单击退出按钮退出该系统。-1. Log in Username: Password yangmingyuan login: 123456 2. physical block number of the user input size can be freely selected. 3. On the page when the input request, please enter the page number and to use successively separated by a space between page numbers, and finally do not have an end other non-numeric character spaces and the like. 4. Then click the Enter button to enter the page number, the pop-up dialog box, click OK OK, and finally click the Start button to begin FIFO paging algorithm. Observation of specific paging and paging process in order paging procedure box, and can be observed that the size and number of pages missing page fault rates. 5. Finally, click the Exit button to exit the system.
Update : 2024-05-17 Size : 2372608 Publisher : yangmingyuan
【Driver Develop】 fifo DL : 0: 使用外部fifo，CY7C68013A USB芯片-readme.txt for FX2_to_extsyncFIFO GPIF FIFO Transactions Auto mode see GPIF Primer section on design examples for operating instructions and details
Update : 2024-05-17 Size : 804864 Publisher : 许晨瑞
【Software Engineering】 FIFO-Verification-Environment-_-Ayutam-Solutions_ DL : 0: this the verification environment for fifo using uvm-this is the verification environment for fifo using uvm
Update : 2024-05-17 Size : 1676288 Publisher : mgokul177
【VHDL-FPGA-Verilog】 fifo DL : 0: 关于FIFO的verilog源代码,可以很快的对FIFO做简单的了解-Verilog on the FIFO source code, you can quickly do a simple understanding of FIFO
Update : 2024-05-17 Size : 237568 Publisher : zx
【VHDL-FPGA-Verilog】 FIFO DL : 0: 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, hoping to help readers
Update : 2024-05-17 Size : 2048 Publisher : huawei
【VHDL-FPGA-Verilog】 fifo DL : 0: 异步FIFO的verilog实现，可以参考一下-Verilog asynchronous FIFO implementation, you can refer to
Update : 2024-05-17 Size : 51200 Publisher : kobe

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