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Synchronous-FIFO

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-11-02
  • Size : 4kb
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  • Author :刘东辉
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Introduction - If you have any usage issues, please Google them yourself
FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT, which is a FIFO data buffer, it is the difference between ordinary memory is no external write address lines, so very convenient to use, but the drawback is that only the order read and write data, the data read by the internal address pointer is automatically incremented by 1 to complete the FIFO main function is based on the dual-port RAM read and write control to complete, resulting in empty status full signal based on data stored in the dual-port RAM. Refers to the dual-port RAM can simultaneously read and write RAM RAM memory
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Synchronous FIFO\mp_tb.vhd
................\Ram_FIFO.vhd
................\Ram_FIFOtest.vhd
Synchronous FIFO
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