A full adder with non-uniform csa

Lab # 4
.......\18 bit csa
.......\..........\1bitmux.txt
.......\..........\fulladder.txt
.......\..........\3bitmux.txt
.......\..........\3bitfulladder.txt
.......\..........\16bitcsa.txt
.......\..........\4bitmux.txt
.......\..........\4bitfulladder.txt
.......\..........\5bitmux.txt
.......\..........\6bitmux.txt
.......\..........\testbench.txt
.......\..........\6bitfulladder.txt
.......\..........\5bitadder.txt
.......\..........\Modelsimcodes
.......\..........\.............\bit_3adder
.......\..........\.............\..........\verilog.asm
.......\..........\.............\..........\_primary.dat
.......\..........\.............\..........\_primary.vhd
.......\..........\.............\bit_4adder
.......\..........\.............\..........\verilog.asm
.......\..........\.............\..........\_primary.dat
.......\..........\.............\..........\_primary.vhd
.......\..........\.............\bit_5adder
.......\..........\.............\..........\verilog.asm
.......\..........\.............\..........\_primary.dat
.......\..........\.............\..........\_primary.vhd
.......\..........\.............\bit_6adder
.......\..........\.............\..........\verilog.asm
.......\..........\.............\..........\_primary.dat
.......\..........\.............\..........\_primary.vhd
.......\..........\.............\cc
.......\..........\.............\..\verilog.asm
.......\..........\.............\..\_primary.dat
.......\..........\.............\..\_primary.vhd
.......\..........\.............\cc0
.......\..........\.............\...\verilog.asm
.......\..........\.............\...\_primary.dat
.......\..........\.............\...\_primary.vhd
.......\..........\.............\cc1
.......\..........\.............\...\verilog.asm
.......\..........\.............\...\_primary.dat
.......\..........\.............\...\_primary.vhd
.......\..........\.............\conventional
.......\..........\.............\............\verilog.asm
.......\..........\.............\............\_primary.dat
.......\..........\.............\............\_primary.vhd
.......\..........\.............\csa_18
.......\..........\.............\......\verilog.asm
.......\..........\.............\......\_primary.dat
.......\..........\.............\......\_primary.vhd
.......\..........\.............\fulladder
.......\..........\.............\.........\verilog.asm
.......\..........\.............\.........\_primary.dat
.......\..........\.............\.........\_primary.vhd
.......\..........\.............\mux
.......\..........\.............\...\verilog.asm
.......\..........\.............\...\_primary.dat
.......\..........\.............\...\_primary.vhd
.......\..........\.............\mux3
.......\..........\.............\....\verilog.asm
.......\..........\.............\....\_primary.dat
.......\..........\.............\....\_primary.vhd
.......\..........\.............\mux_1
.......\..........\.............\.....\verilog.asm
.......\..........\.............\.....\_primary.dat
.......\..........\.............\.....\_primary.vhd
.......\..........\.............\mux_3
.......\..........\.............\.....\verilog.asm
.......\..........\.............\.....\_primary.dat
.......\..........\.............\.....\_primary.vhd
.......\..........\.............\mux_4
.......\..........\.............\.....\verilog.asm
.......\..........\.............\.....\_primary.dat
.......\..........\.............\.....\_primary.vhd
.......\..........\.............\mux_5
.......\..........\.............\.....\verilog.asm
.......\..........\.............\.....\_primary.dat
.......\..........\.............\.....\_primary.vhd
.......\..........\.............\mux_6
.......\..........\.............\.....\verilog.asm
.......\..........\.............\.....\_primary.dat
.......\..........\.............\.....\_primary.vhd
.......\..........\.............\muxaa
.......\..........\.............\.....\verilog.asm
.......\..........\.............\.....\_primary.dat
.......\..........\.............\.....\_primary.vhd
.......\..........\.............\test
.......\..........\..

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