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【Other Embeded program】 verilog source DL : 0: verilog的源代码。给出来常用的一些例程，对于verilog的使用和学习都有很大的帮助作用。-Verilog source code. Out to some routines commonly used for the use and Verilog study has been very helpful.
Update : 2024-05-06 Size : 176128 Publisher : 林伟
【Other】 cpu的VERILOG描述 DL : 0: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Update : 2024-05-06 Size : 369664 Publisher : 陈俊
【VHDL-FPGA-Verilog】用Verilog HDL实现I2C总线功能 DL : 1: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Update : 2024-05-06 Size : 120832 Publisher : 胡路听
【Crack Hack】 MD5(verilog) DL : 0: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Update : 2024-05-06 Size : 4096 Publisher : 张雷
【VHDL-FPGA-Verilog】 des-verilog DL : 1: des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Update : 2024-05-06 Size : 67584 Publisher : 杨云丰
【Other】《Verilog黄金指南》中文翻译版 DL : 0: Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法-Verilog learning materials, they simply PLD development language, and to highlight the key Verilog syntax
Update : 2024-05-06 Size : 468992 Publisher : 张
【VHDL-FPGA-Verilog】 Verilog HDL设计练习进阶 DL : 0: 初学verilog HDL时找的好资料大家共享-Beginners should try to find a good share information
Update : 2024-05-06 Size : 680960 Publisher : chencsw
【VHDL-FPGA-Verilog】 hjs Verilog DL : 0: 是verilog例子。初级适用。包括了简单的例子。-example. The initial application. Including a simple example.
Update : 2024-05-06 Size : 39936 Publisher : 黄先生
【VHDL-FPGA-Verilog】 Verilog DHL数字钟 DL : 0: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Update : 2024-05-06 Size : 2048 Publisher : 谢树扬
【Books】 A Verilog HDL Test Bench Primer DL : 0: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Update : 2024-05-06 Size : 57344 Publisher : 陈正一
【VHDL-FPGA-Verilog】八位的伪随机数产生的verilog文件 DL : 0: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback- shift-register
Update : 2024-05-06 Size : 2048 Publisher : 陈正一
【Books】 Verilog Modeling DL : 0: verilog语言建模资料，从网上整理的，-Verilog language modeling information collated from the Internet.
Update : 2024-05-06 Size : 7168 Publisher : 陈正一
【VHDL-FPGA-Verilog】 verilog实例 DL : 0: 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.
Update : 2024-05-06 Size : 165888 Publisher : 叶若寒
【VHDL-FPGA-Verilog】 Verilog-statemachine DL : 0: 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
Update : 2024-05-06 Size : 183296 Publisher : 张厂
【Other】 Verilog-r2-wangzhengxiong DL : 0: 学些verilog语言的入门书籍，由汪正雄编写，内容挺全的，可以作为初学者的手册。-up some Verilog language entry books, prepared by Hongzhengxiong, as Ting-wide and can serve as a beginner's manual.
Update : 2024-05-06 Size : 401408 Publisher :
【Other】 arm7-verilog DL : 1: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Update : 2024-05-06 Size : 37888 Publisher : 王云
【VHDL-FPGA-Verilog】 Verilog-HDL DL : 0: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Update : 2024-05-06 Size : 784384 Publisher : 东子
【Other Embeded program】 trafficLight-verilog DL : 0: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Update : 2024-05-06 Size : 1532928 Publisher : 王越
【VHDL-FPGA-Verilog】 CRC-Verilog DL : 0: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Update : 2024-05-06 Size : 3072 Publisher : 藏瑞
【VHDL-FPGA-Verilog】 verilog-som DL : 0: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Update : 2024-05-06 Size : 5120 Publisher : 刘索山

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