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【VHDL-FPGA-Verilog】 vga2 DL : 0: 本功能主要实现了VGA的显示，分辨率为1024*768，包内有制作好的coe文件存入rom，适合xilinx芯片-This function is mainly to achieve a VGA display with a resolution of 1024* 768, the bag has produced a good coe file into the rom, for xilinx chip
Update : 2024-04-30 Size : 705536 Publisher : liyi
【VHDL-FPGA-Verilog】 write DL : 0: 使用golang生成一个coe文件，初始化rom。其中随机产生10000个数值作为初始化值-Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 10000
Update : 2024-04-30 Size : 1024 Publisher :
【Software Engineering】 sin_rom DL : 0: 在rom文件中生成正弦波COE文件，在Matlab中生成正余弦波形的浮点值，并量化为16bit定点波形数值- Generate sine wave COE file in rom file
Update : 2024-04-30 Size : 11264 Publisher : 缪国锋
【Communication】 SOES-master DL : 0: Simple Open Source EtherCAT Slave ==== SOES (Simple OpenSource EtherCAT Slave Stack) is an opensource slave stack that is very easy to use and provides a small footprint. It is a good alternative to more complex stacks on the market. Overview SOES is an EtherCAT slave stack written in c. Its purpose is to learn and to use. All users are invited to study the source to get an understanding how an EtherCAT slave functions. Features as of 1.0.0: - Address offset based HAL for easy ESC read/write access via any interface - Mailbox with data link layer - CoE - Object dictionary - SDO read and write for all sizes including segmented transfers - Easy portable C-code suited for embedded applications - Fixed PDO mapping - FoE with bootstrap template - Support for Little and Big endian targets. - Polling for interrupts -Simple Open Source EtherCAT Slave ==== SOES (Simple OpenSource EtherCAT Slave Stack) is an opensource slave stack that is very easy to use and provides a small footprint. It is a good alternative to more complex stacks on the market. Overview SOES is an EtherCAT slave stack written in c. Its purpose is to learn and to use. All users are invited to study the source to get an understanding how an EtherCAT slave functions. Features as of 1.0.0: - Address offset based HAL for easy ESC read/write access via any interface - Mailbox with data link layer - CoE - Object dictionary - SDO read and write for all sizes including segmented transfers - Easy portable C-code suited for embedded applications - Fixed PDO mapping - FoE with bootstrap template - Support for Little and Big endian targets. - Polling for interrupts
Update : 2024-04-30 Size : 196608 Publisher : 吕其铮
【SCM】 HT66F50-io-test DL : 0: HT66F50 IO test sample coe -HT66F50 IO test sample coe
Update : 2024-04-30 Size : 19456 Publisher : 張自強
【Software Engineering】 firfilterPmatlabPfpga DL : 0: FIR滤波器的matlab仿真，使用子函数编程（非fdatool）并产生ISE中FIR核的.coe文件-FIR matlab coe文件
Update : 2024-04-30 Size : 122880 Publisher : dfdqzp
【VHDL-FPGA-Verilog】 firfilterPfpga DL : 0: FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
Update : 2024-04-30 Size : 9401344 Publisher : dfdqzp
【Internet-Network】 Simple Open EtherCAT DL : 1: EtherCAT协议的开源实现，包括EtherCAT主站和从站(EtherCAT Master using SOEM Freescale i.MX53 Blackfin 5xx Blackfin 6xx Intel EtherCAT Slave using SOES Freescale K10 - using Beckhoff ET1100 Freescale K60 - using Beckhoff ET1100 Xilinx Zynq - using Beckhoff ET1815 Supported profiles/features CANOpen over EtherCAT (CoE) Vendor over EtherCAT (VoE) Distributed clocks SERCOS over EtherCAT (SoE))
Update : 2024-04-30 Size : 899072 Publisher : 卡丘流形
【Other】 61505 DL : 0: The following Matlab project contains the source code and Matlab examples used for jpeg image to .coe file. This file is used to convert a jpeg image to . The source code and files included in this project are listed in the project files section, please make sure whether the listed source code meet your needs there.
Update : 2024-04-30 Size : 1024 Publisher : jatcniy
【Other】 ECD DL : 0: A very informative coe on ECD
Update : 2024-04-30 Size : 379904 Publisher : adii
【transportation applications】 coe_from_rv1 DL : 0: % 此函数由初始轨道的位置和速度矢量轨道参数 % %参考资料: % Howard D.Curtis 《Obital Mechanics for Engineering Students》 % P158-164 4.4 Orbital elements and the state vector % 参考代码：P606-608 D.8 coe_from_sv.m %常量： % mu - 地球引力常数 (398600.5 km^3/s^2) % Re - 地球半径 (6378.13655km) % % %输入： % R0 - 初始位置矢量 % V0 - 初始速度矢量 %输出： % coe - 输出的轨道要素 [h_p ecc Omiga i w f] % 其中 % h_p - 轨道近地点高度 (km) % ecc - 偏心率 % Omiga - 升交点赤经(°) % i - 轨道倾角(°) % w - 近地点幅角(°) % f - 真近点角(This function convert orbit position and velocity vector to 6 orbit parameter)
Update : 2024-04-30 Size : 1024 Publisher : unpiorge
【Open-source hardware】 Arduino_20150411 DL : 0: ArduCAT是Arduino Compatible 开发板。本产品力图通过Arduino技术，大大简化EtherCAT从站的开发。ArduCAT开发板包含两路可用于EtherCAT实时以太网的100BASE-TX网口，所以它特别适合基于PC的自动化方案。ArduCAT使用ATMega1280 处理器，兼容Arduino Mega开发板，并具有完全相同的引脚定义。板上采用开关稳压器提供5V 或3.3V的2A直流输出，且发热甚微。除配套的开源Arduino库外，还配有从站应用层代码自动生成工具，用户只需编辑EXCEL表格便生成完整的协议栈，大大简化了通信协议的代码的开发，使用户能够将注意力集中在开发具体的应用上。(The ArduCAT is an Arduino Compatible board aiming to ease the EtherCAT slave device development with the Arduino technology. The board provides 2 100BASE-TX ports for EtherCAT real-time data link which is ideal for PC-based automation. Using ATMega1280 processor, it is compatible with Arduino Mega board, having the same pin definition. The switching regulator on board can source up to 2A current at 5V or 3.3V with mere heat dissipation. The open source software library (https://github.com/ethercat-diy/arducat.git) and slave stack code generation tool that come with the board support the EtherCAT PDO and CoE function, which make developers concentrate on the application code, simplifying the work on hardware and protocol stack.)
Update : 2024-04-30 Size : 514048 Publisher : 小二了
【Education soft system】 Cordys CoE SAP Connector 2.0.3 DL : 0: the cordys connector java version 2
Update : 2024-04-30 Size : 944128 Publisher : mizouuuu
【VHDL-FPGA-Verilog】 ethernet_loopback DL : 0: 通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
Update : 2024-04-30 Size : 23942144 Publisher : marktuwen
【matlab】 fwdadsplabcodes9and10 DL : 0: filter adaptive matlab coe
Update : 2024-04-30 Size : 4680704 Publisher : jainuddin
【matlab】 guide compresion DL : 0: La imagen reconstruida a partir de los coecientes de la DCT representa la imagen comprimida, que debera mostrarse en la pantalla. Las variaciones en la calidad de la imagen observada reejaran la eliminacion de los diferentes componentes obtenidos durante la etapa de la transformada del coseno, siguiendo los principios del estandard.
Update : 2024-04-30 Size : 263168 Publisher : tdi_van
【SCM】 EtherCAT_Slave_C_Code DL : 1: 直接可用的ethercat从站代码，带有canopen协议。C语言实现(ethercat slave code .you can use it easily! recommend to download.)
Update : 2024-04-30 Size : 334848 Publisher : 易水寒一世
【ARM-PowerPC-ColdFire-MIPS】 LPC2148_4 (3 DL : 0: for beginqdpfdfdf thi s coe will bw useful
Update : 2024-04-30 Size : 421888 Publisher : jeevan123
【VHDL-FPGA-Verilog】 CIC DL : 0: 包括地址产生单元、数据查询单元（可以重新初始化rom中的数据，由matlab产生.coe文件替换）、积分单元、抽取单元、梳状滤波单元，对于初学者很有帮助(Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb filter unit, is very helpful for beginners.)
Update : 2024-04-30 Size : 5120 Publisher : 午后河流

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