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【Software Engineering】 rom DL : 0: tk25平台默认的是128Mbit flash memory 和 32Mbit SRAM，因为1BYTE等于8BIT，所以就是我们通常所说的是16M ROM和4M RAM，不过由于文件系统占用2M，这2M一般又被分为系统盘和用户盘，系统盘存储NV文件和MMS相关文件，对用户不可见，-tk25 platform, the default is 128Mbit flash memory and 32Mbit SRAM, because the 1BYTE equal 8BIT, so that we usually are talking about 16M ROM and 4M RAM, but because the file system occupied by 2M, which generally has been divided into 2M system disk and user disk , the system disk storage NV files and MMS related documents, the user is not visible,
Update : 2024-05-08 Size : 2048 Publisher : sky
【Software Engineering】 spartan6_fpga_blockram_user_guide DL : 0: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Update : 2024-05-08 Size : 376832 Publisher : james
【Other】 ApexLogo11b DL : 0: dvd rom editer tools this tool editing rom bin logo enconding
Update : 2024-05-08 Size : 19456 Publisher : nilesh
【Other】 PICkit2v2.61.00SetupA DL : 0: PicKit is tool to read and write on PIC ROM
Update : 2024-05-08 Size : 4129792 Publisher : Thach
【VHDL-FPGA-Verilog】 ROM DL : 0: ROM模块，功能在于，是创建一个简易的rom模块-rom
Update : 2024-05-08 Size : 2048 Publisher : henin
【VHDL-FPGA-Verilog】 rom DL : 0: A ROM to build a squaring circuit
Update : 2024-05-08 Size : 1024 Publisher : Ahmed
【Mathimatics-Numerical algorithms】 NDimensionalCardinal(CatmullRom)SplineInterpolatio DL : 0: N-Dimensional Cardinal(Catmull-Rom) Spline Interpolation
Update : 2024-05-08 Size : 14336 Publisher : 肖才子
【VHDL-FPGA-Verilog】 emny DL : 0: cpld/fpga vhdl语言rom 引用的简单例子-cpld/fpga vhdl language rom cited a simple example
Update : 2024-05-08 Size : 400384 Publisher : chen
【OS program】 CD-Rom DL : 0: vb 光驱控制可以控制计算机光驱开关-vb drive control switch can control a computer CD-ROM
Update : 2024-05-08 Size : 14336 Publisher : 李琴
【Multimedia Develop】 AbrirCerrar_CD-Rom DL : 0: Behavior Lingo que permite abrir-cerrar el CD-ROM de la PC desde una multimedia en Macromedia Director.
Update : 2024-05-08 Size : 1024 Publisher : RuberHG
【ARM-PowerPC-ColdFire-MIPS】 YLP2450_DVK_USER_CD_V13 DL : 0: S3C2450开发板的全套光盘，包括OrCAD格式原理图、PADS格式封装库、BSP源码包、烧录下载工具和软件，用户手册，编程文档和芯片规格书等等。-S3C2450 development board complete set of CD-ROM format, including OrCAD schematics, PADS format package library, BSP source package, burn download the tools and software, user manuals, programming documentation and chip specifications and so on.
Update : 2024-05-08 Size : 33401856 Publisher : cmosttl
【VHDL-FPGA-Verilog】 ROM DL : 0: ROM在FPGA内的实现方法，简单的例程-ROM
Update : 2024-05-08 Size : 321536 Publisher : zhou
【DSP program】 BlueCore6-ROMdatasheet DL : 0: Full datasheet for CSR BlueCore6-ROM. Advance Information Data Sheet for BC63B239A September 2007
Update : 2024-05-08 Size : 1720320 Publisher : mika000
【VHDL-FPGA-Verilog】 BS DL : 0: 用EDA设计ROM和RAM及其应用，用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display
Update : 2024-05-08 Size : 13039616 Publisher : 黄奇家
【SCM】 rom DL : 0: 基于51单片机在keil下编程，rom初始化程序-51 MCU-based programming in keil under, rom initialization procedure
Update : 2024-05-08 Size : 10240 Publisher : hu
【Windows Develop】 LFSR DL : 0: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Update : 2024-05-08 Size : 870400 Publisher : 风影
【Windows Mobile】 P505_V31371_ITA DL : 0: Boot loader and Rom asus P505 Palm.
Update : 2024-05-08 Size : 28565504 Publisher : Pal620poc
【VHDL-FPGA-Verilog】 VHDL(sin) DL : 0: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Update : 2024-05-08 Size : 17408 Publisher : 爱好
【Database system】 ROM DL : 0: FPGA内部储存，源代码。 FPGA内部储存，源代码。-FPGA
Update : 2024-05-08 Size : 1315840 Publisher : tandongfei
【SCM】 proteus DL : 0: Proteus6.7 是目前最好的模拟单片机外围器件的工具，真的很不错。可以仿真 51 系列、AVR，PIC 等常用的 MCU 及其外围电路（如 LCD，RAM，ROM，键盘，马达，LED，AD/DA，部分 SPI 器件，部分 IIC 器件 -Proteus6.7 is the best tool for simulation of microcontroller peripherals, really good. Can be simulated 51, AVR, PIC and other commonly used MCU and its peripheral circuits (such as the LCD, RAM, ROM, keyboard, motors, LED, AD/DA, part of the SPI devices, part of the IIC device
Update : 2024-05-08 Size : 1352704 Publisher : 杨云

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