DDS, FPGA generated using Verilog language

dds_quicklogic
..............\CLAADD8S.SCH
..............\CLAADD8S.TRE
..............\CLAADD8S.V
..............\CSAC1.SCH
..............\CSAC1.SYM
..............\CSALOWC1.SCH
..............\CSALOWC1.SYM
..............\DDS.V
..............\DDSPA.TF
..............\DDSPM.TF
..............\LOADFW.V
..............\LOADPW.V
..............\PHASEA.V
..............\PHASEMOD.V
..............\PNGEN.V
..............\ROMTAB.V
..............\SINLUP.V

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