The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock

Altera
......\elec_clk_project
......\................\.cdtbuild
......\................\.cdtproject
......\................\.project
......\................\altera_avalon_pio_reg.h
......\................\application.stf
......\................\Debug
......\................\elec_clk.cpp
......\................\LCD.h
......\................\readme.txt
......\elec_clk_project_syslib
......\.......................\.cdtbuild
......\.......................\.cdtproject
......\.......................\.project
......\.......................\Debug
......\.......................\readme.txt
......\.......................\system.stf
......\NiosII_lab
......\..........\avalon_pwm.v
......\..........\button_pio.v
......\..........\cfi_flash.log
......\..........\clk_nios.bsf
......\..........\clk_nios.ptf
......\..........\clk_nios.ptf.bak
......\..........\clk_nios.v
......\..........\clk_nios_generation_script
......\..........\clk_nios_log.txt
......\..........\clk_nios_setup_quartus.tcl
......\..........\clk_nios_sim
......\..........\............\atail-f.pl
......\..........\............\dummy_file
......\..........\............\jtag_uart_input_mutex.dat
......\..........\............\jtag_uart_input_stream.dat
......\..........\............\jtag_uart_output_stream.dat
......\..........\cmp_state.ini
......\..........\cpu.ocp
......\..........\cpu.v
......\..........\cpu_ic_tag_ram.mif
......\..........\cpu_jtag_debug_module.v
......\..........\cpu_jtag_debug_module_wrapper.v
......\..........\cpu_ociram_default_contents.mif
......\..........\cpu_rf_ram_a.mif
......\..........\cpu_rf_ram_b.mif
......\..........\cpu_test_bench.v
......\..........\crc.bdf
......\..........\crc_mux.bdf
......\..........\crc_peripheral.v
......\..........\crc_peripheral.vhd
......\..........\custominstruction_cpu.vhd
......\..........\db
......\..........\..\altsyncram_3vd1.tdf
......\..........\..\altsyncram_4vd1.tdf
......\..........\..\altsyncram_a9e1.tdf
......\..........\..\altsyncram_bp62.tdf
......\..........\..\altsyncram_nll1.tdf
......\..........\..\altsyncram_qmb1.tdf
......\..........\..\altsyncram_s8e1.tdf
......\..........\..\altsyncram_stv1.tdf
......\..........\..\a_dpfifo_ml21.tdf
......\..........\..\a_fefifo_7cf.tdf
......\..........\..\cntr_9c7.tdf
......\..........\..\cntr_rd8.tdf
......\..........\..\decode_ogi.tdf
......\..........\..\dpram_j921.tdf
......\..........\..\NiosII_lab.asm.qmsg
......\..........\..\NiosII_lab.cbx.xml
......\..........\..\NiosII_lab.cmp.cdb
......\..........\..\NiosII_lab.cmp.hdb
......\..........\..\NiosII_lab.cmp.kpt
......\..........\..\NiosII_lab.cmp.logdb
......\..........\..\NiosII_lab.cmp.rdb
......\..........\..\NiosII_lab.cmp.tdb
......\..........\..\NiosII_lab.cmp0.ddb
......\..........\..\NiosII_lab.dbp
......\..........\..\NiosII_lab.db_info
......\..........\..\NiosII_lab.eco.cdb
......\..........\..\NiosII_lab.fit.qmsg
......\..........\..\NiosII_lab.hier_info
......\..........\..\NiosII_lab.hif
......\..........\..\NiosII_lab.map.cdb
......\..........\..\NiosII_lab.map.hdb
......\..........\..\NiosII_lab.map.logdb
......\..........\..\NiosII_lab.map.qmsg
......\..........\..\NiosII_lab.pre_map.cdb
......\..........\..\NiosII_lab.pre_map.hdb
......\..........\..\NiosII_lab.psp
......\..........\..\NiosII_lab.rtlv.hdb
......\..........\..\NiosII_lab.rtlv_sg.cdb
......\..........\..\NiosII_lab.rtlv_sg_swap.cdb
......\..........\..\NiosII_lab.sgdiff.cdb
......\..........\..\NiosII_lab.sgdiff.hdb
......\..........\..\NiosII_lab.signalprobe.cdb
......\..........\..\NiosII_lab.sld_design_entry.sci
......\..........\..\NiosII_lab.sld_design_entry_dsc.sci
......\..........\..\NiosII_lab.smp_dump.txt
......\..........\..\NiosII_lab.syn_hier_info
......\..........\..\NiosII_lab.tan.qmsg
......\..........\..\scfifo_ff21.tdf
......\..........\endian_convert.bdf

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