32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.

寄存器堆
........\decoder.v
........\decodertest.v
........\dff.v
........\dfftest.v
........\mux_32.v
........\mux_32test.v
........\register.v
........\registerfile.v
........\registerfiletest.v
........\registertest.v

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