To Quatus Ⅱ as a platform, the use of VHDL language digital code lock function, you can realize simulation.

LOCK
....\Chain1.cdf
....\cmp_state.ini
....\DB
....\..\lock.asm.qmsg
....\..\lock.asm_labs.ddb
....\..\lock.cbx.xml
....\..\lock.cmp.cdb
....\..\lock.cmp.hdb
....\..\lock.cmp.logdb
....\..\lock.cmp.rdb
....\..\lock.cmp.tdb
....\..\lock.cmp0.ddb
....\..\lock.db_info
....\..\lock.eco.cdb
....\..\lock.fit.qmsg
....\..\lock.hier_info
....\..\LOCK.HIF
....\..\lock.map.cdb
....\..\lock.map.hdb
....\..\lock.map.logdb
....\..\lock.map.qmsg
....\..\lock.pre_map.cdb
....\..\lock.pre_map.hdb
....\..\LOCK.PSP
....\..\lock.rtlv.hdb
....\..\lock.rtlv_sg.cdb
....\..\lock.rtlv_sg_swap.cdb
....\..\lock.sgdiff.cdb
....\..\lock.sgdiff.hdb
....\..\lock.signalprobe.cdb
....\..\lock.sld_design_entry.sci
....\..\lock.sld_design_entry_dsc.sci
....\..\lock.syn_hier_info
....\..\lock.tan.qmsg
....\..\lock_cmp.qrpt
....\lock.asm.rpt
....\lock.done
....\lock.fit.eqn
....\lock.fit.rpt
....\lock.fit.summary
....\lock.flow.rpt
....\lock.map.eqn
....\lock.map.rpt
....\lock.map.summary
....\LOCK.PIN
....\LOCK.POF
....\LOCK.QPF
....\LOCK.QSF
....\LOCK.QWS
....\LOCK.SOF
....\lock.tan.rpt
....\lock.tan.summary
....\LOCK.VHD
....\LOCK.VWF

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