FPGA development of Verilog HDL entry procedures- water lights, the real available, authentication is passed, the project environment for Altera Quartus

flowled
.......\db
.......\..\add_sub_msh.tdf
.......\..\flowled.analyze_file.qmsg
.......\..\flowled.asm.qmsg
.......\..\flowled.cbx.xml
.......\..\flowled.cmp.cdb
.......\..\flowled.cmp.hdb
.......\..\flowled.cmp.kpt
.......\..\flowled.cmp.logdb
.......\..\flowled.cmp.rdb
.......\..\flowled.cmp.tdb
.......\..\flowled.cmp0.ddb
.......\..\flowled.dbp
.......\..\flowled.db_info
.......\..\flowled.eco.cdb
.......\..\flowled.eds_overflow
.......\..\flowled.fit.qmsg
.......\..\flowled.fnsim.hdb
.......\..\flowled.fnsim.qmsg
.......\..\flowled.hier_info
.......\..\flowled.hif
.......\..\flowled.map.cdb
.......\..\flowled.map.hdb
.......\..\flowled.map.logdb
.......\..\flowled.map.qmsg
.......\..\flowled.pre_map.cdb
.......\..\flowled.pre_map.hdb
.......\..\flowled.psp
.......\..\flowled.rtlv.hdb
.......\..\flowled.rtlv_sg.cdb
.......\..\flowled.rtlv_sg_swap.cdb
.......\..\flowled.sgdiff.cdb
.......\..\flowled.sgdiff.hdb
.......\..\flowled.signalprobe.cdb
.......\..\flowled.sim.hdb
.......\..\flowled.sim.qmsg
.......\..\flowled.sim.rdb
.......\..\flowled.sim_ori.vwf
.......\..\flowled.sld_design_entry.sci
.......\..\flowled.sld_design_entry_dsc.sci
.......\..\flowled.syn_hier_info
.......\..\flowled.tan.qmsg
.......\..\wed.zsf
.......\flowled.asm.rpt
.......\flowled.cdf
.......\flowled.done
.......\flowled.dpf
.......\flowled.fit.rpt
.......\flowled.fit.smsg
.......\flowled.fit.summary
.......\flowled.flow.rpt
.......\flowled.map
.......\flowled.map.rpt
.......\flowled.map.smsg
.......\flowled.map.summary
.......\flowled.pin
.......\flowled.pof
.......\flowled.qpf
.......\flowled.qsf
.......\flowled.qws
.......\flowled.sim.rpt
.......\flowled.sof
.......\flowled.tan.rpt
.......\flowled.tan.summary
.......\flowled.v
.......\flowled.vwf
.......\output_file.map

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