sdram test controller altera

sdram
.....\doc
.....\readme_sdr_sdram.txt
.....\ref-sdr-sdram-verilog.zip
.....\sdr_sdram.pdf
.....\simulation
.....\..........\sdr_sdram_tb.v
.....\source
.....\......\altclklock.v
.....\......\Command.v
.....\......\compile_all.v
.....\......\control_interface.v
.....\......\Params.v
.....\......\PLL1.v
.....\......\sdr_data_path.v
.....\......\sdr_sdram.v

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