CAN bus IPCORE, using Verilog HDL language.

bench
.....\verilog
.....\.......\can_testbench.v
.....\.......\can_testbench_defines.v
.....\.......\CVS
.....\.......\...\Entries
.....\.......\...\Repository
.....\.......\...\Root
.....\.......\timescale.v
rtl
...\verilog
...\.......\can_acf.v
...\.......\can_bsp.v
...\.......\can_btl.v
...\.......\can_crc.v
...\.......\can_defines.v
...\.......\can_fifo.v
...\.......\can_ibo.v
...\.......\can_register.v
...\.......\can_registers.v
...\.......\can_register_asyn.v
...\.......\can_register_asyn_syn.v
...\.......\can_register_syn.v
...\.......\can_top.v
...\.......\CVS
...\.......\...\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\README.txt

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